[Mlir-commits] [mlir] 2f94ce0 - [mlir][DeclarativeParser] Move several missed parsers over to the declarative form.
River Riddle
llvmlistbot at llvm.org
Sat Feb 8 15:52:51 PST 2020
Author: River Riddle
Date: 2020-02-08T15:47:55-08:00
New Revision: 2f94ce0dcfd1f827105ac3d53d870447a25d57a3
URL: https://github.com/llvm/llvm-project/commit/2f94ce0dcfd1f827105ac3d53d870447a25d57a3
DIFF: https://github.com/llvm/llvm-project/commit/2f94ce0dcfd1f827105ac3d53d870447a25d57a3.diff
LOG: [mlir][DeclarativeParser] Move several missed parsers over to the declarative form.
Differential Revision: https://reviews.llvm.org/D74283
Added:
Modified:
mlir/include/mlir/Dialect/LoopOps/LoopOps.td
mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td
mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td
mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td
mlir/lib/Dialect/LoopOps/LoopOps.cpp
mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
mlir/test/Dialect/SPIRV/ops.mlir
Removed:
################################################################################
diff --git a/mlir/include/mlir/Dialect/LoopOps/LoopOps.td b/mlir/include/mlir/Dialect/LoopOps/LoopOps.td
index a2d718db13e8..0d6ee5f3d830 100644
--- a/mlir/include/mlir/Dialect/LoopOps/LoopOps.td
+++ b/mlir/include/mlir/Dialect/LoopOps/LoopOps.td
@@ -249,6 +249,7 @@ def ReduceReturnOp :
}];
let arguments = (ins AnyType:$result);
+ let assemblyFormat = "$result attr-dict `:` type($result)";
}
def TerminatorOp : Loop_Op<"terminator", [Terminator]> {
diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td
index 5f2c030566e1..4dfc439a3404 100644
--- a/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td
@@ -23,7 +23,8 @@ class SPV_BitBinaryOp<string mnemonic, list<OpTrait> traits = []> :
[NoSideEffect, SameOperandsAndResultType])>;
class SPV_BitFieldExtractOp<string mnemonic, list<OpTrait> traits = []> :
- SPV_Op<mnemonic, !listconcat(traits, [NoSideEffect])> {
+ SPV_Op<mnemonic, !listconcat(traits,
+ [NoSideEffect, AllTypesMatch<["base", "result"]>])> {
let arguments = (ins
SPV_ScalarOrVectorOf<SPV_Integer>:$base,
SPV_Integer:$offset,
@@ -34,9 +35,11 @@ class SPV_BitFieldExtractOp<string mnemonic, list<OpTrait> traits = []> :
SPV_ScalarOrVectorOf<SPV_Integer>:$result
);
- let parser = [{ return ::parseBitFieldExtractOp(parser, result); }];
- let printer = [{ ::printBitFieldExtractOp(this->getOperation(), p); }];
- let verifier = [{ return ::verifyBitFieldExtractOp(this->getOperation()); }];
+ let verifier = [{ return success(); }];
+
+ let assemblyFormat = [{
+ operands attr-dict `:` type($base) `,` type($offset) `,` type($count)
+ }];
}
class SPV_BitUnaryOp<string mnemonic, list<OpTrait> traits = []> :
diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td
index ebbf83817cb6..ac95214b6184 100644
--- a/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td
@@ -333,8 +333,7 @@ def SPV_MergeOp : SPV_Op<"_merge", [Terminator]> {
let results = (outs);
- let parser = [{ return parseNoIOOp(parser, result); }];
- let printer = [{ printNoIOOp(getOperation(), p); }];
+ let assemblyFormat = "attr-dict";
let hasOpcode = 0;
@@ -360,8 +359,7 @@ def SPV_ReturnOp : SPV_Op<"Return", [InFunctionScope, Terminator]> {
let results = (outs);
- let parser = [{ return parseNoIOOp(parser, result); }];
- let printer = [{ printNoIOOp(getOperation(), p); }];
+ let assemblyFormat = "attr-dict";
}
// -----
@@ -383,8 +381,7 @@ def SPV_UnreachableOp : SPV_Op<"Unreachable", [InFunctionScope, Terminator]> {
let results = (outs);
- let parser = [{ return parseNoIOOp(parser, result); }];
- let printer = [{ printNoIOOp(getOperation(), p); }];
+ let assemblyFormat = "attr-dict";
}
// -----
diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td
index 995e5d4fcf86..d4d181b78a2d 100644
--- a/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td
@@ -365,8 +365,7 @@ def SPV_ModuleEndOp : SPV_Op<"_module_end", [InModuleScope, Terminator]> {
let results = (outs);
- let parser = [{ return parseNoIOOp(parser, result); }];
- let printer = [{ printNoIOOp(getOperation(), p); }];
+ let assemblyFormat = "attr-dict";
let verifier = [{ return success(); }];
diff --git a/mlir/lib/Dialect/LoopOps/LoopOps.cpp b/mlir/lib/Dialect/LoopOps/LoopOps.cpp
index 3dd999dcdea7..1ce3bbfd0875 100644
--- a/mlir/lib/Dialect/LoopOps/LoopOps.cpp
+++ b/mlir/lib/Dialect/LoopOps/LoopOps.cpp
@@ -418,22 +418,6 @@ static LogicalResult verify(ReduceReturnOp op) {
return success();
}
-static ParseResult parseReduceReturnOp(OpAsmParser &parser,
- OperationState &result) {
- OpAsmParser::OperandType operand;
- Type resultType;
- if (parser.parseOperand(operand) || parser.parseColonType(resultType) ||
- parser.resolveOperand(operand, resultType, result.operands))
- return failure();
-
- return success();
-}
-
-static void print(OpAsmPrinter &p, ReduceReturnOp op) {
- p << op.getOperationName() << " " << op.result() << " : "
- << op.result().getType();
-}
-
//===----------------------------------------------------------------------===//
// TableGen'd op method definitions
//===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
index 8aa99b1b0300..0475d31b865e 100644
--- a/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
+++ b/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
@@ -488,41 +488,6 @@ namespace {
// Common parsers and printers
//===----------------------------------------------------------------------===//
-static ParseResult parseBitFieldExtractOp(OpAsmParser &parser,
- OperationState &state) {
- SmallVector<OpAsmParser::OperandType, 3> operandInfo;
- Type baseType;
- Type offsetType;
- Type countType;
- auto loc = parser.getCurrentLocation();
-
- if (parser.parseOperandList(operandInfo, 3) || parser.parseColon() ||
- parser.parseType(baseType) || parser.parseComma() ||
- parser.parseType(offsetType) || parser.parseComma() ||
- parser.parseType(countType) ||
- parser.resolveOperands(operandInfo, {baseType, offsetType, countType},
- loc, state.operands)) {
- return failure();
- }
- state.addTypes(baseType);
- return success();
-}
-
-static void printBitFieldExtractOp(Operation *op, OpAsmPrinter &printer) {
- printer << op->getName() << ' ' << op->getOperands() << " : "
- << op->getOperandTypes();
-}
-
-static LogicalResult verifyBitFieldExtractOp(Operation *op) {
- if (op->getOperand(0).getType() != op->getResult(0).getType()) {
- return op->emitError("expected the same type for the first operand and "
- "result, but provided ")
- << op->getOperand(0).getType() << " and "
- << op->getResult(0).getType();
- }
- return success();
-}
-
// Parses an atomic update op. If the update op does not take a value (like
// AtomicIIncrement) `hasValue` must be false.
static ParseResult parseAtomicUpdateOp(OpAsmParser &parser,
@@ -668,19 +633,6 @@ static LogicalResult verifyGroupNonUniformArithmeticOp(Operation *groupOp) {
return success();
}
-// Parses an op that has no inputs and no outputs.
-static ParseResult parseNoIOOp(OpAsmParser &parser, OperationState &state) {
- if (parser.parseOptionalAttrDict(state.attributes))
- return failure();
- return success();
-}
-
-// Prints an op that has no inputs and no outputs.
-static void printNoIOOp(Operation *op, OpAsmPrinter &printer) {
- printer << op->getName();
- printer.printOptionalAttrDict(op->getAttrs());
-}
-
static ParseResult parseUnaryOp(OpAsmParser &parser, OperationState &state) {
OpAsmParser::OperandType operandInfo;
Type type;
diff --git a/mlir/test/Dialect/SPIRV/ops.mlir b/mlir/test/Dialect/SPIRV/ops.mlir
index 64779d18ed5e..d5098723360c 100644
--- a/mlir/test/Dialect/SPIRV/ops.mlir
+++ b/mlir/test/Dialect/SPIRV/ops.mlir
@@ -257,7 +257,7 @@ func @bit_field_u_extract_vec(%base: vector<3xi32>, %offset: i8, %count: i8) ->
// -----
func @bit_field_u_extract_invalid_result_type(%base: vector<3xi32>, %offset: i32, %count: i16) -> vector<4xi32> {
- // expected-error @+1 {{expected the same type for the first operand and result, but provided 'vector<3xi32>' and 'vector<4xi32>'}}
+ // expected-error @+1 {{failed to verify that all of {base, result} have same type}}
%0 = "spv.BitFieldUExtract" (%base, %offset, %count) : (vector<3xi32>, i32, i16) -> vector<4xi32>
spv.ReturnValue %0 : vector<4xi32>
}
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