[Mlir-commits] [mlir] 8affe88 - [mlir][PDL] Use .getOperation() when construction SuccessorRange to avoid ambiguous constructor in GCC5
River Riddle
llvmlistbot at llvm.org
Tue Dec 1 18:15:47 PST 2020
Author: River Riddle
Date: 2020-12-01T18:13:27-08:00
New Revision: 8affe88108a1d5f37303cb2128e0650e70ab1eae
URL: https://github.com/llvm/llvm-project/commit/8affe88108a1d5f37303cb2128e0650e70ab1eae
DIFF: https://github.com/llvm/llvm-project/commit/8affe88108a1d5f37303cb2128e0650e70ab1eae.diff
LOG: [mlir][PDL] Use .getOperation() when construction SuccessorRange to avoid ambiguous constructor in GCC5
Added:
Modified:
mlir/lib/Rewrite/ByteCode.cpp
Removed:
################################################################################
diff --git a/mlir/lib/Rewrite/ByteCode.cpp b/mlir/lib/Rewrite/ByteCode.cpp
index 972f5097d4e7..33a754bb3c07 100644
--- a/mlir/lib/Rewrite/ByteCode.cpp
+++ b/mlir/lib/Rewrite/ByteCode.cpp
@@ -529,7 +529,7 @@ void Generator::generate(pdl_interp::AreEqualOp op, ByteCodeWriter &writer) {
writer.append(OpCode::AreEqual, op.lhs(), op.rhs(), op.getSuccessors());
}
void Generator::generate(pdl_interp::BranchOp op, ByteCodeWriter &writer) {
- writer.append(OpCode::Branch, SuccessorRange(op));
+ writer.append(OpCode::Branch, SuccessorRange(op.getOperation()));
}
void Generator::generate(pdl_interp::CheckAttributeOp op,
ByteCodeWriter &writer) {
@@ -637,8 +637,9 @@ void Generator::generate(pdl_interp::RecordMatchOp op, ByteCodeWriter &writer) {
ByteCodeField patternIndex = patterns.size();
patterns.emplace_back(PDLByteCodePattern::create(
op, rewriterToAddr[op.rewriter().getLeafReference()]));
- writer.append(OpCode::RecordMatch, patternIndex, SuccessorRange(op),
- op.matchedOps(), op.inputs());
+ writer.append(OpCode::RecordMatch, patternIndex,
+ SuccessorRange(op.getOperation()), op.matchedOps(),
+ op.inputs());
}
void Generator::generate(pdl_interp::ReplaceOp op, ByteCodeWriter &writer) {
writer.append(OpCode::ReplaceOp, op.operation(), op.replValues());
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