[Mlir-commits] [mlir] ab64fd3 - Allow single-bit integer types to have signs. A signed one bit integer is either 0 or -1.

[Chris Lattner]

Author: Chris Lattner
Date: 2020-04-09T15:23:06-07:00
New Revision: ab64fd39d252ec8ddeee7fa73e2534f4b7c079bc

URL: https://github.com/llvm/llvm-project/commit/ab64fd39d252ec8ddeee7fa73e2534f4b7c079bc
DIFF: https://github.com/llvm/llvm-project/commit/ab64fd39d252ec8ddeee7fa73e2534f4b7c079bc.diff

LOG: Allow single-bit integer types to have signs.  A signed one bit integer is either 0 or -1.

Reviewers: rriddle!

Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, grosul1, frgossen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77832

Added: 
    

Modified: 
    mlir/lib/IR/AsmPrinter.cpp
    mlir/lib/IR/StandardTypes.cpp
    mlir/test/IR/attribute.mlir
    mlir/test/IR/invalid.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/lib/IR/AsmPrinter.cpp b/mlir/lib/IR/AsmPrinter.cpp
index beaf4c0792fb..175339c5b1f3 100644
--- a/mlir/lib/IR/AsmPrinter.cpp
+++ b/mlir/lib/IR/AsmPrinter.cpp
@@ -1291,11 +1291,12 @@ void ModulePrinter::printAttribute(Attribute attr,
     break;
   case StandardAttributes::Integer: {
     auto intAttr = attr.cast<IntegerAttr>();
-    // Print all signed/signless integer attributes as signed unless i1.
-    bool isSigned =
-        attrType.isIndex() || (!attrType.isUnsignedInteger() &&
-                               attrType.getIntOrFloatBitWidth() != 1);
-    intAttr.getValue().print(os, isSigned);
+    // Only print attributes as unsigned if they are explicitly unsigned or are
+    // signless 1-bit values.  Indexes, signed values, and multi-bit signless
+    // values print as signed.
+    bool isUnsigned =
+        attrType.isUnsignedInteger() || attrType.isSignlessInteger(1);
+    intAttr.getValue().print(os, !isUnsigned);
 
     // IntegerAttr elides the type if I64.
     if (typeElision == AttrTypeElision::May && attrType.isSignlessInteger(64))

diff  --git a/mlir/lib/IR/StandardTypes.cpp b/mlir/lib/IR/StandardTypes.cpp
index cff65e734752..36ad0b4000eb 100644
--- a/mlir/lib/IR/StandardTypes.cpp
+++ b/mlir/lib/IR/StandardTypes.cpp
@@ -103,8 +103,6 @@ IntegerType::verifyConstructionInvariants(Location loc, unsigned width,
     return emitError(loc) << "integer bitwidth is limited to "
                           << IntegerType::kMaxWidth << " bits";
   }
-  if (width == 1 && signedness != IntegerType::Signless)
-    return emitOptionalError(loc, "cannot have signedness semantics for i1");
   return success();
 }
 

diff  --git a/mlir/test/IR/attribute.mlir b/mlir/test/IR/attribute.mlir
index 3e4f0db65942..1980e7a7eec7 100644
--- a/mlir/test/IR/attribute.mlir
+++ b/mlir/test/IR/attribute.mlir
@@ -79,7 +79,12 @@ func @int_attrs_pass() {
     // CHECK-SAME: attr_18 = 9223372036854775807 : si64
     attr_18 = 9223372036854775807 : si64,
     // CHECK-SAME: attr_19 = 18446744073709551615 : ui64
-    attr_19 = 18446744073709551615 : ui64
+    attr_19 = 18446744073709551615 : ui64,
+    // CHECK-SAME: attr_20 = 1 : ui1
+    attr_20 = 1: ui1,
+    // CHECK-SAME: attr_21 = -1 : si1
+    attr_21 = -1: si1
+
   } : () -> ()
 
   return

diff  --git a/mlir/test/IR/invalid.mlir b/mlir/test/IR/invalid.mlir
index cbd97cd63b54..255f6cc79fe1 100644
--- a/mlir/test/IR/invalid.mlir
+++ b/mlir/test/IR/invalid.mlir
@@ -200,14 +200,6 @@ func @illegaltype(i0) // expected-error {{invalid integer width}}
 
 // -----
 
-func @illegaltype(ui1) // expected-error {{cannot have signedness semantics for i1}}
-
-// -----
-
-func @illegaltype(si1) // expected-error {{cannot have signedness semantics for i1}}
-
-// -----
-
 func @malformed_for_percent() {
   affine.for i = 1 to 10 { // expected-error {{expected SSA operand}}