[Mlir-commits] [mlir] 06ddb79 - [MLIR] Add missing colon after CHECKs.

[Christian Sigg]

Author: Christian Sigg
Date: 2020-04-08T11:16:06+02:00
New Revision: 06ddb7946bb18b9340d0033f5c2d16fb0e075291

URL: https://github.com/llvm/llvm-project/commit/06ddb7946bb18b9340d0033f5c2d16fb0e075291
DIFF: https://github.com/llvm/llvm-project/commit/06ddb7946bb18b9340d0033f5c2d16fb0e075291.diff

LOG: [MLIR] Add missing colon after CHECKs.

Reviewers: herhut

Reviewed By: herhut

Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, grosul1, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77709

Added: 
    

Modified: 
    mlir/test/IR/memory-ops.mlir
    mlir/test/Target/llvmir.mlir
    mlir/test/Transforms/canonicalize.mlir
    mlir/test/Transforms/memref-bound-check.mlir
    mlir/test/Transforms/pipeline-data-transfer.mlir
    mlir/test/mlir-tblgen/pattern.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/test/IR/memory-ops.mlir b/mlir/test/IR/memory-ops.mlir
index 6a03a91df3c8..f44ab1c873be 100644
--- a/mlir/test/IR/memory-ops.mlir
+++ b/mlir/test/IR/memory-ops.mlir
@@ -111,8 +111,8 @@ func @dma_ops() {
   // DMA with strides
   dma_start %A[%c0], %Ah[%c0], %num_elements, %tag[%c0], %stride, %elt_per_stride : memref<256 x f32>, memref<256 x f32, 1>, memref<1 x f32>
   dma_wait %tag[%c0], %num_elements : memref<1 x f32>
-  // CHECK-NEXT  dma_start %0[%c0], %1[%c0], %c256, %2[%c0], %c32, %c16 : memref<256xf32>, memref<256xf32, 1>, memref<1xf32>
-  // CHECK-NEXT  dma_wait %2[%c0], %c256 : memref<1xf32>
+  // CHECK-NEXT:  dma_start %0[%c0], %1[%c0], %c256, %2[%c0], %c32, %c16 : memref<256xf32>, memref<256xf32, 1>, memref<1xf32>
+  // CHECK-NEXT:  dma_wait %2[%c0], %c256 : memref<1xf32>
 
   return
 }

diff  --git a/mlir/test/Target/llvmir.mlir b/mlir/test/Target/llvmir.mlir
index 3909a8a31228..e3a918572590 100644
--- a/mlir/test/Target/llvmir.mlir
+++ b/mlir/test/Target/llvmir.mlir
@@ -1202,7 +1202,7 @@ llvm.func @callFenceInst() {
   llvm.return
 }
 
-// CHECK-LABEL @passthrough
+// CHECK-LABEL: @passthrough
 // CHECK: #[[ATTR_GROUP:[0-9]*]]
 llvm.func @passthrough() attributes {passthrough = ["noinline", ["alignstack", "4"], "null-pointer-is-valid", ["foo", "bar"]]} {
   llvm.return

diff  --git a/mlir/test/Transforms/canonicalize.mlir b/mlir/test/Transforms/canonicalize.mlir
index d323bc474d06..e5e3af2724eb 100644
--- a/mlir/test/Transforms/canonicalize.mlir
+++ b/mlir/test/Transforms/canonicalize.mlir
@@ -370,7 +370,7 @@ func @dead_dealloc_fold_multi_use(%cond : i1) {
 
 // CHECK-LABEL: func @dead_block_elim
 func @dead_block_elim() {
-  // CHECK-NOT ^bb
+  // CHECK-NOT: ^bb
   func @nested() {
     return
 

diff  --git a/mlir/test/Transforms/memref-bound-check.mlir b/mlir/test/Transforms/memref-bound-check.mlir
index 5f8c43b4e344..76ed78a76240 100644
--- a/mlir/test/Transforms/memref-bound-check.mlir
+++ b/mlir/test/Transforms/memref-bound-check.mlir
@@ -56,8 +56,8 @@ func @test_mod_floordiv_ceildiv() {
       %idy1 = affine.apply affine_map<(d0, d1, d2) -> (d1 floordiv 4)>(%i, %j, %j)
       %idy2 = affine.apply affine_map<(d0, d1, d2) -> (d2 ceildiv 4 - 1)>(%i, %j, %j)
       affine.store %x, %A[%idy0, %idy1, %idy2] : memref<128 x 64 x 64 x i32> // expected-error {{'affine.store' op memref out of lower bound access along dimension #3}}
-    } // CHECK }
-  } // CHECK }
+    } // CHECK: }
+  } // CHECK: }
   return
 }
 
@@ -82,7 +82,7 @@ func @test_no_out_of_bounds() {
       %x  = affine.load %A[%idx0, %zero] : memref<257 x 256 x i32>
       %idy = affine.apply affine_map<(d0, d1) -> (d0 floordiv 256)>(%i, %i)
       %y  = affine.load %B[%idy] : memref<1 x i32>
-    } // CHECK-NEXT }
+    } // CHECK-NEXT: }
   }
   return
 }

diff  --git a/mlir/test/Transforms/pipeline-data-transfer.mlir b/mlir/test/Transforms/pipeline-data-transfer.mlir
index 842c1d6210e7..3c93cc8ced68 100644
--- a/mlir/test/Transforms/pipeline-data-transfer.mlir
+++ b/mlir/test/Transforms/pipeline-data-transfer.mlir
@@ -136,7 +136,7 @@ func @loop_dma_nested(%arg0: memref<512x32xvector<8xf32>>, %arg1: memref<512x32x
     // CHECK: [[TAG_ARG1:%[0-9]+]] = alloc() : memref<2x2xi32>
     // CHECK: affine.dma_start %{{.*}}[
     // CHECK: affine.dma_start %{{.*}}[
-    // CHECK-NEXT affine.for %{{.*}} = 1 to 8 {
+    // CHECK-NEXT: affine.for %{{.*}} = 1 to 8 {
     affine.for %i1 = 0 to 8 {
       %7 = affine.apply #map1(%i0, %i1)
       %8 = affine.apply #map2(%i1)

diff  --git a/mlir/test/mlir-tblgen/pattern.mlir b/mlir/test/mlir-tblgen/pattern.mlir
index a96d90f4ed2c..d06cdba3ae42 100644
--- a/mlir/test/mlir-tblgen/pattern.mlir
+++ b/mlir/test/mlir-tblgen/pattern.mlir
@@ -32,7 +32,7 @@ func @verifyZeroResult(%arg0 : i32) {
   return
 }
 
-// CHECK-LABEL verifyZeroArg
+// CHECK-LABEL: verifyZeroArg
 func @verifyZeroArg() -> i32 {
   // CHECK: "test.op_k"() : () -> i32
   %0 = "test.op_j"() : () -> i32