[llvm-testresults] buildbot failure in lab.llvm.org on phase2 - living

llvmlab-buildmaster at lab.llvm.org llvmlab-buildmaster at lab.llvm.org
Fri Jun 13 11:03:55 PDT 2014 

The Buildbot has detected a new failure on builder phase2 - living while building lab.llvm.org.
Full details are available at:
 http://lab.llvm.org:8013/builders/phase2%20-%20living/builds/187

Buildbot URL: http://lab.llvm.org:8013/

Buildslave for this Build: macpro1

Build Reason: scheduler
Build Source Stamp: 210908
Blamelist: chapuni,dsanders,mcinally,sbenza,tnorthover,zjovanovic

BUILD FAILED: failed

sincerely,
 -The Buildbot


================================================================================

CHANGES:
File: lib/Target/X86/X86InstrAVX512.td
On: smooshlab-project
At: Fri 13 Jun 2014 04:50:38
Changed By: mcinally
Comments: Add HasCDI predicate to AVX512 VPBROADCASTM*.
Properties: 
  phase_id: r210892-t20140613_045238-b836



File: test/CodeGen/X86/fast-isel-args-fail2.ll
On: smooshlab-project
At: Fri 13 Jun 2014 05:16:38
Changed By: chapuni
Comments: llvm/test/CodeGen/X86/fast-isel-args-fail2.ll: Don't expect to fail with -Asserts. It might or might not crash.Properties: 
  phase_id: r210894-t20140613_051838-b837



File: utils/not/not.cpp
On: smooshlab-project
At: Fri 13 Jun 2014 05:36:38
Changed By: chapuni
Comments: [Win32] Let utils/not aware of abort(), aka llvm_unreachable(), in msvcrt.

It has exit code as 3. abort(), aka unreachable, may be handled as crash.

FIXME: Could we move this into Win32/Program.inc?Properties: 
  phase_id: r210895-t20140613_053838-b838



Files:
 lib/Target/Mips/Mips64InstrInfo.td
 lib/Target/Mips/Mips64r6InstrInfo.td
 test/MC/Mips/mips2/invalid-mips3-wrong-error.s
 test/MC/Mips/mips2/invalid-mips3.s
 test/MC/Mips/mips3/valid.s
 test/MC/Mips/mips4/valid.s
 test/MC/Mips/mips5/valid.s
 test/MC/Mips/mips64/valid.s
 test/MC/Mips/mips64r2/valid.s
 test/MC/Mips/mips64r6/invalid-mips64.s
On: smooshlab-project
At: Fri 13 Jun 2014 06:00:38
Changed By: dsanders
Comments: [mips][mips64r6] daddi is not available on MIPS64r6

Summary:
It's not emitted by the code generator so we only need assembler tests.

Also added missing daddi aliases from dsub mnemonics, and removed a couple
duplicate dsub tests.

Depends on D4112

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4113Properties: 
  phase_id: r210897-t20140613_060238-b839



Files:
 lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
 lib/Target/Mips/Mips32r6InstrFormats.td
 lib/Target/Mips/Mips32r6InstrInfo.td
 lib/Target/Mips/MipsInstrInfo.td
 lib/Target/Mips/MipsLongBranch.cpp
 test/MC/Mips/mips1/valid.s
 test/MC/Mips/mips2/valid.s
 test/MC/Mips/mips3/valid.s
 test/MC/Mips/mips32/valid.s
 test/MC/Mips/mips32r2/valid.s
 test/MC/Mips/mips32r6/valid.s
 test/MC/Mips/mips4/valid.s
 test/MC/Mips/mips5/valid.s
 test/MC/Mips/mips64/valid.s
 test/MC/Mips/mips64r2/valid.s
 test/MC/Mips/mips64r6/invalid-mips1.s
 test/MC/Mips/mips64r6/invalid-mips2.s
 test/MC/Mips/mips64r6/invalid-mips3.s
 test/MC/Mips/mips64r6/invalid-mips4.s
 test/MC/Mips/mips64r6/invalid-mips5.s
 test/MC/Mips/mips64r6/invalid-mips64.s
 test/MC/Mips/mips64r6/valid.s
On: smooshlab-project
At: Fri 13 Jun 2014 06:16:38
Changed By: dsanders
Comments: [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction

Summary:
b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias
for 'bgezal $zero, $offset') still remains with the same encoding it had
prior to MIPS32r6/MIPS64r6.

Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the
MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo.

No changes were required to the CodeGen test that looks for BAL
(test/CodeGen/Mips/longbranch.ll) since the new instruction has the same
syntax.

Depends on D4113

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4114Properties: 
  phase_id: r210898-t20140613_061838-b840



Files:
 lib/Target/Mips/Mips32r6InstrInfo.td
 test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
 test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
On: smooshlab-project
At: Fri 13 Jun 2014 06:20:37
Changed By: dsanders
Comments: [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6

Summary:
These MIPS-3D instructions have never been implemented in LLVM so we only
add testcases.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4115Properties: 
  phase_id: r210900-t20140613_062954-b841



Files:
 lib/Target/Mips/Disassembler/MipsDisassembler.cpp
 lib/Target/Mips/Mips32r6InstrFormats.td
 lib/Target/Mips/Mips32r6InstrInfo.td
 lib/Target/Mips/MipsInstrFPU.td
 lib/Target/Mips/MipsInstrFormats.td
 lib/Target/Mips/MipsInstrInfo.td
 test/MC/Mips/mips3/valid.s
 test/MC/Mips/mips32/valid.s
 test/MC/Mips/mips32r2/valid.s
 test/MC/Mips/mips32r6/valid.s
 test/MC/Mips/mips4/valid.s
 test/MC/Mips/mips5/valid.s
 test/MC/Mips/mips64/valid.s
 test/MC/Mips/mips64r2/valid.s
 test/MC/Mips/mips64r6/valid.s
On: smooshlab-project
At: Fri 13 Jun 2014 06:26:37
Changed By: dsanders
Comments: [mips] Add cache and pref instructions

Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116Properties: 
  phase_id: r210900-t20140613_062954-b841



File: test/CodeGen/X86/avx512-intrinsics.ll
On: smooshlab-project
At: Fri 13 Jun 2014 06:30:37
Changed By: mcinally
Comments: Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.
Properties: 
  phase_id: r210901-t20140613_064041-b842



Files:
 lib/AST/ASTContext.cpp
 unittests/ASTMatchers/ASTMatchersTest.cpp
On: smooshlab-project
At: Fri 13 Jun 2014 06:40:37
Changed By: sbenza
Comments: Do not store duplicate parents when memoization data is available.

Summary:
Do not store duplicate parents when memoization data is available.
This does not solve the duplication problem, but ameliorates it.

Reviewers: klimek

Subscribers: klimek, cfe-commits

Differential Revision: http://reviews.llvm.org/D4124Properties: 
  phase_id: r210902-t20140613_065134-b843



Files:
 docs/Atomics.rst
 docs/LangRef.rst
 include/llvm/CodeGen/ISDOpcodes.h
 include/llvm/CodeGen/SelectionDAG.h
 include/llvm/CodeGen/SelectionDAGNodes.h
 include/llvm/IR/Instructions.h
 lib/AsmParser/LLLexer.cpp
 lib/AsmParser/LLParser.cpp
 lib/AsmParser/LLToken.h
 lib/Bitcode/Reader/BitcodeReader.cpp
 lib/Bitcode/Writer/BitcodeWriter.cpp
 lib/CodeGen/AtomicExpandLoadLinkedPass.cpp
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeTypes.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
 lib/CodeGen/TargetLoweringBase.cpp
 lib/IR/AsmWriter.cpp
 lib/IR/Instruction.cpp
 lib/IR/Instructions.cpp
 lib/Target/CppBackend/CPPBackend.cpp
 lib/Target/X86/X86ISelLowering.cpp
 lib/Transforms/IPO/MergeFunctions.cpp
 lib/Transforms/Instrumentation/ThreadSanitizer.cpp
 lib/Transforms/Scalar/LowerAtomic.cpp
 test/Assembler/atomic.ll
 test/Bitcode/atomic.ll
 test/Bitcode/memInstructions.3.2.ll
 test/Bitcode/weak-cmpxchg-upgrade.ll
 test/Bitcode/weak-cmpxchg-upgrade.ll.bc
 test/CodeGen/AArch64/arm64-atomic-128.ll
 test/CodeGen/AArch64/arm64-atomic.ll
 test/CodeGen/AArch64/atomic-ops.ll
 test/CodeGen/AArch64/cmpxchg-idioms.ll
 test/CodeGen/ARM/atomic-64bit.ll
 test/CodeGen/ARM/atomic-cmp.ll
 test/CodeGen/ARM/atomic-op.ll
 test/CodeGen/ARM/atomic-ops-v8.ll
 test/CodeGen/ARM/cmpxchg-idioms.ll
 test/CodeGen/CPP/atomic.ll
 test/CodeGen/Mips/atomic.ll
 test/CodeGen/Mips/atomicops.ll
 test/CodeGen/PowerPC/Atomics-32.ll
 test/CodeGen/PowerPC/atomic-1.ll
 test/CodeGen/PowerPC/atomic-2.ll
 test/CodeGen/R600/atomic_cmp_swap_local.ll
 test/CodeGen/SPARC/atomics.ll
 test/CodeGen/SystemZ/cmpxchg-01.ll
 test/CodeGen/SystemZ/cmpxchg-02.ll
 test/CodeGen/SystemZ/cmpxchg-03.ll
 test/CodeGen/SystemZ/cmpxchg-04.ll
 test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
 test/CodeGen/X86/Atomics-64.ll
 test/CodeGen/X86/atomic_op.ll
 test/CodeGen/X86/coalescer-remat.ll
 test/Instrumentation/MemorySanitizer/atomics.ll
 test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll
 test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll
 test/Transforms/LowerAtomic/atomic-swap.ll
On: smooshlab-project
At: Fri 13 Jun 2014 07:36:37
Changed By: tnorthover
Comments: IR: add "cmpxchg weak" variant to support permitted failure.

This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.

As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.

At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.

By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.

Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.

Summary for out of tree users:
------------------------------

+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.Properties: 
  phase_id: r210908-t20140613_073837-b844



File: docs/LangRef.rst
On: smooshlab-project
At: Fri 13 Jun 2014 07:36:37
Changed By: tnorthover
Comments: Docs: fix grammar error in descriptionProperties: 
  phase_id: r210908-t20140613_073837-b844



File: docs/LangRef.rst
On: smooshlab-project
At: Fri 13 Jun 2014 07:36:37
Changed By: tnorthover
Comments: Docs: remove extra {} around result types.

It makes the types look like they're single-element structures. And
when we have instructions that *do* result in a struct, that can get
confusing rather quickly.Properties: 
  phase_id: r210908-t20140613_073837-b844



File: test/CodeGen/atomic-ops.c
On: smooshlab-project
At: Fri 13 Jun 2014 07:36:37
Changed By: tnorthover
Comments: Tests: use CHECK-LABEL to help debugging failuresProperties: 
  phase_id: r210908-t20140613_073837-b844



Files:
 lib/CodeGen/CGAtomic.cpp
 lib/CodeGen/CGBuiltin.cpp
 lib/CodeGen/CGExprScalar.cpp
 test/CodeGen/Atomics.c
 test/CodeGen/atomic-ops.c
 test/CodeGen/atomic.c
On: smooshlab-project
At: Fri 13 Jun 2014 07:36:37
Changed By: tnorthover
Comments: IR-change: cmpxchg operations now return { iN, i1 }.

This is a minimal fix for clang. I'll soon add support for generating
weak variants when requested, but that's not really necessary for the
LLVM change in isolation.Properties: 
  phase_id: r210908-t20140613_073837-b844



Files:
 lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
 lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
 lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
 lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
 lib/Target/Mips/MipsInstrInfo.td
 test/MC/Mips/mips64r6/relocations.s
On: smooshlab-project
At: Fri 13 Jun 2014 07:36:37
Changed By: zjovanovic
Comments: [mips][mips64r6] Relocation R_MIPS_PC18_S3
Differential Revision: http://reviews.llvm.org/D3890
Properties: 
  phase_id: r210908-t20140613_073837-b844



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