[llvm-testresults] buildbot failure in lab.llvm.org on phase1 - sanity

[llvmlab-buildmaster at lab.llvm.org]

The Buildbot has detected a new failure on builder phase1 - sanity while building llvm.
Full details are available at:
 http://lab.llvm.org:8013/builders/phase1%20-%20sanity/builds/2318

Buildbot URL: http://lab.llvm.org:8013/

Buildslave for this Build: macpro1

Build Reason: scheduler
Build Source Stamp: 213248
Blamelist: kongyi,tnorthover

BUILD FAILED: failed

sincerely,
 -The Buildbot


================================================================================

CHANGES:
Files:
 include/llvm/IR/IntrinsicsAArch64.td
 lib/Target/AArch64/AArch64InstrFormats.td
 lib/Target/AArch64/AArch64InstrInfo.td
 test/CodeGen/AArch64/intrinsics-memory-barrier.ll
On: http://10.1.1.2/svn/llvm-project
For: llvm
At: Thu 17 Jul 2014 04:01:38
Changed By: kongyi
Comments: Port memory barriers intrinsics to AArch64

Memory barrier __builtin_arm_[dmb, dsb, isb] intrinsics are required to
implement their corresponding ACLE and MSVC intrinsics.

This patch ports ARM dmb, dsb, isb intrinsic to AArch64.

Differential Revision: http://reviews.llvm.org/D4520
Properties: 




Files:
 docs/LangRef.rst
 include/llvm/CodeGen/ISDOpcodes.h
 include/llvm/IR/Intrinsics.td
 include/llvm/Target/TargetSelectionDAG.td
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeTypes.h
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
 lib/Target/AArch64/AArch64InstrInfo.td
 lib/Target/ARM/ARMISelLowering.cpp
 lib/Target/ARM/ARMInstrVFP.td
 lib/Target/NVPTX/NVPTXIntrinsics.td
 lib/Target/R600/SIInstructions.td
 lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86InstrSSE.td
 test/CodeGen/AArch64/arm64-vcvt_f.ll
 test/CodeGen/AArch64/f16-convert.ll
 test/CodeGen/ARM/fp16.ll
 test/CodeGen/R600/fp16_to_fp32.ll
 test/CodeGen/R600/fp32_to_fp16.ll
 test/CodeGen/X86/cvt16.ll
On: http://10.1.1.2/svn/llvm-project
For: llvm
At: Thu 17 Jul 2014 04:01:38
Changed By: tnorthover
Comments: CodeGen: extend f16 conversions to permit types > float.

This makes the two intrinsics @llvm.convert.from.f16 and
@llvm.convert.to.f16 accept types other than simple "float". This is
only strictly needed for the truncate operation, since otherwise
double rounding occurs and there's no way to represent the strict IEEE
conversion. However, for symmetry we allow larger types in the extend
too.

During legalization, we can expand an "fp16_to_double" operation into
two extends for convenience, but abort when the truncate isn't legal. A new
libcall is probably needed here.

Even after this commit, various target tweaks are needed to actually use the
extended intrinsics. I've put these into separate commits for clarity, so there
are no actual tests of f64 conversion here.Properties: 




LOGS: