[llvm-testresults] buildbot failure in lab.llvm.org on phase2 - living

[llvmlab-buildmaster at lab.llvm.org]

The Buildbot has detected a new failure on builder phase2 - living while building lab.llvm.org.
Full details are available at:
 http://lab.llvm.org:8013/builders/phase2%20-%20living/builds/6721

Buildbot URL: http://lab.llvm.org:8013/

Buildslave for this Build: macpro1

Build Reason: scheduler
Build Source Stamp: 199114
Blamelist: dwmw2,lattner,rsandifo,tnorthover

BUILD FAILED: failed

sincerely,
 -The Buildbot


================================================================================

CHANGES:
Files:
 lib/Target/X86/X86FloatingPoint.cpp
 lib/Target/X86/X86FrameLowering.cpp
 lib/Target/X86/X86InstrControl.td
 lib/Target/X86/X86InstrFormats.td
 lib/Target/X86/X86InstrInfo.td
 test/MC/X86/ret.s
On: smooshlab-project
At: Mon 13 Jan 2014 06:17:00
Changed By: dwmw2
Comments: [x86] Fix retq/retl handling in 64-bit mode

This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.

LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:

asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");

cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.

I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.Properties: 
  phase_id: r199114-t20140113_073504-b15551



File: lib/Target/ARM/ARMInstrThumb.td
On: smooshlab-project
At: Mon 13 Jan 2014 06:27:00
Changed By: tnorthover
Comments: ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.

Previously we only used GPR for the destination placeholder in "ldr rD, [pc,
incorrect codegen under the integrated assembler.

This should fix both issues (which probably only affect MachO targets at the
moment).

rdar://problem/15800156Properties: 
  phase_id: r199114-t20140113_073504-b15551



File: test/CodeGen/ARM/thumb-litpool.ll
On: smooshlab-project
At: Mon 13 Jan 2014 06:31:01
Changed By: tnorthover
Comments: ARM: add test for r199108. Oops.

rdar://problem/15800156Properties: 
  phase_id: r199114-t20140113_073504-b15551



File: include/llvm/Bitcode/BitcodeWriterPass.h
On: smooshlab-project
At: Mon 13 Jan 2014 07:21:00
Changed By: lattner
Comments: fix a -Wdocumentation warning.
Properties: 
  phase_id: r199114-t20140113_073504-b15551



Files:
 lib/Target/SystemZ/SystemZISelLowering.cpp
 lib/Target/SystemZ/SystemZISelLowering.h
 test/CodeGen/SystemZ/shift-10.ll
On: smooshlab-project
At: Mon 13 Jan 2014 07:27:00
Changed By: rsandifo
Comments: [SystemZ] Optimize (sext (ashr (shl ...), ...))

...into (ashr (shl (anyext X), ...), ...), which requires one fewer
instruction.  The (anyext X) can sometimes be simplified too.

I didn't do this in DAGCombiner because widening shifts isn't a win
on all targets.
Properties: 
  phase_id: r199114-t20140113_073504-b15551



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