[llvm-testresults] buildbot failure in smooshlab on llvm-gcc-x86_64-darwin10-selfhost

[daniel_dunbar at apple.com]

The Buildbot has detected a new failure of llvm-gcc-x86_64-darwin10-selfhost on smooshlab.
Full details are available at:
 http://smooshlab.apple.com:8010/builders/llvm-gcc-x86_64-darwin10-selfhost/builds/6311

Buildbot URL: http://smooshlab.apple.com:8010/

Buildslave for this Build: smoosh-04

Build Reason: 
Build Source Stamp: 117904
Blamelist: lattner,resistor,void

BUILD FAILED: failed test-llvm

sincerely,
 -The Buildbot


================================================================================

CHANGES:
File: utils/TableGen/AsmMatcherEmitter.cpp
At: Sun 31 Oct 2010 21:57:37
Changed By: lattner
Comments: refactor initialization of InstructionInfo to be sharable between
instructions and InstAliases.  Start creating InstructionInfo's
for Aliases.
Properties: 




File: utils/TableGen/AsmMatcherEmitter.cpp
At: Sun 31 Oct 2010 22:12:37
Changed By: lattner
Comments: rename InstructionInfo -> MatchableInfo since it now
represents InstAliases as well.  Rename 
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).
Properties: 




Files:
 test/MC/ARM/neon-shift-encoding.ll
 test/MC/ARM/neon-shift-encoding.s
At: Sun 31 Oct 2010 22:27:37
Changed By: resistor
Comments: Convert this test to .s form.
Properties: 




Files:
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 lib/Target/X86/X86InstrInfo.td
 test/MC/X86/x86-64.s
 utils/TableGen/AsmMatcherEmitter.cpp
 utils/TableGen/CodeGenInstruction.cpp
 utils/TableGen/CodeGenInstruction.h
At: Sun 31 Oct 2010 22:37:37
Changed By: lattner
Comments: Implement enough of the missing instalias support to get
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

Properties: 




Files:
 lib/Target/X86/X86InstrInfo.td
 test/MC/X86/x86-64.s
At: Sun 31 Oct 2010 22:48:14
Changed By: lattner
Comments: "mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits.  Support this memory form.
Properties: 




File: test/CodeGen/ARM/arm-and-tst-peephole.ll
At: Sun 31 Oct 2010 22:53:27
Changed By: void
Comments: Disable because peephole is disabled.Properties: 




File: lib/CodeGen/PeepholeOptimizer.cpp
At: Sun 31 Oct 2010 22:53:27
Changed By: void
Comments: The testcase is now XFAILed. Sorry about the breakage.
Properties: 




LOGS:
Last 10 lines of 'stdio':
	********************
	Failing Tests (1):
	    LLVM :: CodeGen/ARM/long_shift.ll
	
	  Expected Passes    : 5509
	  Expected Failures  : 43
	  Unsupported Tests  : 40
	  Unexpected Failures: 1
	make[1]: *** [check-local-lit] Error 1
	make: *** [check] Error 2

Last 10 lines of 'dg.log':
	

Last 10 lines of 'dg.sum':