[llvm-testresults] PowerPC nightly test

[Oscar T. Plant]

http://persephone.cs.uiuc.edu/~oscar/nightlytest/

DEJAGNU TEST RESULTS:
  FAIL: /Users/oscar/buildtest/llvm/test/Regression/CFrontend/2006-01-16-BitCountIntrinsicsUnsigned.c: 
  FAIL: /Users/oscar/buildtest/llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll: 

DEJAGNU STATISTICS:
  # of expected passes		1361
  # of unexpected failures	2
  # of expected failures		35

USERS WHO COMMITTED:
  alenhar2
  evancheng
  lattner
  reid
  resistor

ADDED FILES:
  llvm/test/Regression/CodeGen/Alpha/call_adj.ll
  llvm/test/Regression/CodeGen/X86/2006-05-17-VectorArg.ll

CHANGED FILES:
  llvm/Makefile
  llvm/Makefile.rules
  llvm/include/llvm/Module.h
  llvm/include/llvm/Target/TargetLowering.h
  llvm/include/llvm/Transforms/Utils/Cloning.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Makefile
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMRegisterInfo.h
  llvm/lib/Target/Alpha/Alpha.td
  llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.h
  llvm/lib/Target/IA64/IA64.td
  llvm/lib/Target/IA64/IA64RegisterInfo.cpp
  llvm/lib/Target/IA64/IA64RegisterInfo.h
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/PowerPC/README.txt
  llvm/lib/Target/Sparc/Sparc.td
  llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
  llvm/lib/Target/Sparc/SparcRegisterInfo.h
  llvm/lib/Target/Target.td
  llvm/lib/Target/TargetData.cpp
  llvm/lib/Target/TargetLowering.cpp
  llvm/lib/Target/X86/README.txt
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.h
  llvm/lib/Transforms/Scalar/LowerAllocations.cpp
  llvm/lib/Transforms/Scalar/LowerInvoke.cpp
  llvm/lib/Transforms/Scalar/LowerSelect.cpp
  llvm/lib/Transforms/Scalar/LowerSwitch.cpp
  llvm/lib/Transforms/Scalar/Mem2Reg.cpp
  llvm/lib/Transforms/Utils/CloneModule.cpp
  llvm/lib/VMCore/Module.cpp
  llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll
  llvm/test/Regression/ExecutionEngine/hello2.ll
  llvm/tools/Makefile
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/CodeGenTarget.h
  llvm/utils/TableGen/DAGISelEmitter.cpp
  llvm/utils/TableGen/DAGISelEmitter.h
  llvm/utils/TableGen/RegisterInfoEmitter.cpp