[llvm-testresults] FreeBSD 6.0 BETA4 x86 nightly test (gcc 4.0.2)

[Vladimir Merzliakov]

http://npt.cc.rsu.ru/testresults-X86-FreeBSD/index.html
using LLVM-GCC builded from CVS sources at:
Tue Jan 17 08:41:25 UTC 2006
-------------------------------------------------------
DEJAGNU TEST RESULTS:
  PERFECT!

DEJAGNU STATISTICS:
  # of expected passes		1234
  # of expected failures		36

TESTS FIXED:  

llc-beta /MultiSource/Benchmarks/MallocBench/espresso/espresso



TESTS BROKEN: 

llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc



USERS WHO COMMITTED:
  alenhar2
  duraid
  evancheng
  jeffc
  lattner
  reid
  sampo

ADDED FILES:
  llvm/lib/Target/IA64/IA64Bundling.cpp

CHANGED FILES:
  llvm-poolalloc/lib/PoolAllocate/AccessTrace.cpp
  llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp
  llvm-poolalloc/lib/PoolAllocate/PoolAllocate.cpp
  llvm-poolalloc/lib/PoolAllocate/PoolOptimize.cpp
  llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp
  llvm-test/External/SPEC/CINT2000/252.eon/Makefile
  llvm/docs/BytecodeFormat.html
  llvm/docs/LangRef.html
  llvm/include/llvm/CodeGen/ScheduleDAG.h
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/include/llvm/InlineAsm.h
  llvm/include/llvm/Module.h
  llvm/include/llvm/Target/TargetLowering.h
  llvm/lib/AsmParser/Lexer.cpp
  llvm/lib/AsmParser/Lexer.l
  llvm/lib/AsmParser/ParserInternals.h
  llvm/lib/AsmParser/llvmAsmParser.cpp
  llvm/lib/AsmParser/llvmAsmParser.h
  llvm/lib/AsmParser/llvmAsmParser.y
  llvm/lib/Bytecode/Reader/Reader.cpp
  llvm/lib/Bytecode/Reader/Reader.h
  llvm/lib/Bytecode/Writer/SlotCalculator.cpp
  llvm/lib/Bytecode/Writer/SlotCalculator.h
  llvm/lib/Bytecode/Writer/Writer.cpp
  llvm/lib/Bytecode/Writer/WriterInternals.h
  llvm/lib/CodeGen/DwarfWriter.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Target/Alpha/AlphaISelLowering.cpp
  llvm/lib/Target/Alpha/AlphaISelLowering.h
  llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
  llvm/lib/Target/IA64/IA64.h
  llvm/lib/Target/IA64/IA64ISelLowering.cpp
  llvm/lib/Target/IA64/IA64ISelLowering.h
  llvm/lib/Target/IA64/IA64InstrInfo.cpp
  llvm/lib/Target/IA64/IA64InstrInfo.td
  llvm/lib/Target/IA64/IA64RegisterInfo.cpp
  llvm/lib/Target/IA64/IA64TargetMachine.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
  llvm/lib/Target/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86ISelPattern.cpp
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/lib/VMCore/AsmWriter.cpp
  llvm/lib/VMCore/InlineAsm.cpp
  llvm/lib/VMCore/Module.cpp
  llvm/lib/VMCore/Verifier.cpp
  llvm/test/Feature/inlineasm.ll
  llvm/utils/TableGen/DAGISelEmitter.cpp