[llvm-testresults] Debian GNU/Linux i686 Nightly Test

[Al Stone]

http://www.toolchain.org/~ahs3/Sites/ia32

DEJAGNU TEST RESULTS:
  FAIL: /home/ahs3/llvm/build/llvm/test/Regression/BugPoint/misopt-basictest.ll: 
  FAIL: /home/ahs3/llvm/build/llvm/test/Regression/CFrontend/2004-06-17-UnorderedCompares.c.tr: 
  FAIL: /home/ahs3/llvm/build/llvm/test/Regression/CFrontend/2005-12-04-AttributeUsed.c: 
  FAIL: /home/ahs3/llvm/build/llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c: 
  FAIL: /home/ahs3/llvm/build/llvm/test/Regression/CFrontend/2006-01-16-BitCountIntrinsicsUnsigned.c: 

DEJAGNU STATISTICS:
  # of expected passes		1229
  # of unexpected failures	5
  # of expected failures		36

TESTS FIXED:  

llc-beta /MultiSource/Benchmarks/MallocBench/espresso/espresso



TESTS BROKEN: 

llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc



USERS WHO COMMITTED:
  alenhar2
  duraid
  evancheng
  jeffc
  lattner
  sampo

ADDED FILES:
  llvm/lib/Target/IA64/IA64Bundling.cpp
  llvm/test/Regression/Transforms/ScalarRepl/2006-01-24-IllegalUnionPromoteCrash.ll

CHANGED FILES:
  llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp
  llvm-poolalloc/lib/PoolAllocate/PoolAllocate.cpp
  llvm-test/External/SPEC/CINT2000/252.eon/Makefile
  llvm/include/llvm/CodeGen/ScheduleDAG.h
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/include/llvm/InlineAsm.h
  llvm/include/llvm/Module.h
  llvm/include/llvm/Target/TargetLowering.h
  llvm/lib/Bytecode/Reader/Reader.cpp
  llvm/lib/CodeGen/DwarfWriter.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Target/Alpha/AlphaISelLowering.cpp
  llvm/lib/Target/Alpha/AlphaISelLowering.h
  llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
  llvm/lib/Target/IA64/IA64.h
  llvm/lib/Target/IA64/IA64ISelLowering.cpp
  llvm/lib/Target/IA64/IA64ISelLowering.h
  llvm/lib/Target/IA64/IA64InstrInfo.cpp
  llvm/lib/Target/IA64/IA64InstrInfo.td
  llvm/lib/Target/IA64/IA64RegisterInfo.cpp
  llvm/lib/Target/IA64/IA64TargetMachine.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
  llvm/lib/Target/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86ISelPattern.cpp
  llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
  llvm/lib/VMCore/AsmWriter.cpp
  llvm/lib/VMCore/InlineAsm.cpp
  llvm/lib/VMCore/Module.cpp
  llvm/utils/TableGen/DAGISelEmitter.cpp