[llvm-testresults] Cron <andrewl at fenris> sh /home/andrewl/llvm-alpha.sh

[Cron Daemon]

DEJAGNU TEST RESULTS:
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CodeGen/X86/shift-double.llx: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/ExecutionEngine/2003-01-04-ArgumentBug.ll: 

DEJAGNU STATISTICS:
  # of expected passes		1141
  # of unexpected failures	2
  # of expected failures		33
cvs history: warning: failed to open /home/andrewl/.cvspass for reading: No such file or directory

TESTS FIXED:  

cbe /MultiSource/Benchmarks/MallocBench/espresso/espresso
llc /MultiSource/Benchmarks/MallocBench/espresso/espresso
llc /External/SPEC/CINT95/099.go/099.go



TESTS BROKEN: 

llc /SingleSource/UnitTests/2005-07-17-INT-To-FP
cbe /SingleSource/UnitTests/2005-07-17-INT-To-FP


Warning: empty y range [0:0], adjusting to [-1:1]
Warning: empty y range [0:0], adjusting to [-1:1]
Warning: empty y range [0:0], adjusting to [-1:1]
Warning: empty y range [0:0], adjusting to [-1:1]

USERS WHO COMMITTED:
  duraid
  jeffc
  lattner
  sampo

CHANGED FILES:
  llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/include/llvm/Target/TargetInstrInfo.h
  llvm/lib/CodeGen/ELFWriter.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.h
  llvm/lib/Target/Alpha/AlphaRegisterInfo.td
  llvm/lib/Target/IA64/IA64ISelPattern.cpp
  llvm/lib/Target/IA64/IA64RegisterInfo.cpp
  llvm/lib/Target/IA64/IA64RegisterInfo.h
  llvm/lib/Target/IA64/IA64RegisterInfo.td
  llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
  llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPC32RegisterInfo.h
  llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
  llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
  llvm/lib/Target/Skeleton/SkeletonRegisterInfo.cpp
  llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h
  llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td
  llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
  llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
  llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
  llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
  llvm/lib/Target/Target.td
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.h
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/utils/TableGen/CodeGenInstruction.h
  llvm/utils/TableGen/CodeGenRegisters.h
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/InstrInfoEmitter.cpp
  llvm/utils/TableGen/InstrInfoEmitter.h
  llvm/utils/TableGen/Record.cpp
  llvm/utils/TableGen/Record.h
  llvm/utils/TableGen/RegisterInfoEmitter.cpp
  llvm/win32/x86/x86.vcproj