[llvm-testresults] linux-x86-optimized-2005-08-20

[Reid Spencer]

DEJAGNU TEST RESULTS:
  FAIL: /proj/llvm/nightlytest/build/llvm/test/Regression/CFrontend/2004-11-27-VariableSizeInStructure.c: 
  FAIL: /proj/llvm/nightlytest/build/llvm/test/Regression/CFrontend/2005-07-28-IncorrectWeakGlobal.c: 
  FAIL: /proj/llvm/nightlytest/build/llvm/test/Regression/CodeGen/X86/shift-double.llx: 

DEJAGNU STATISTICS:
  # of expected passes		1140
  # of unexpected failures	3
  # of expected failures		33
ADDED   WARNINGS:
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:: warning: 'TRC' may be used uninitialized in this function


TESTS FIXED:  

compile /SingleSource/UnitTests/2005-07-17-INT-To-FP
llc /SingleSource/UnitTests/2005-07-17-INT-To-FP
cbe /SingleSource/UnitTests/2005-07-17-INT-To-FP
jit /SingleSource/UnitTests/2005-07-17-INT-To-FP
llc-beta /SingleSource/UnitTests/2005-07-17-INT-To-FP



USERS WHO COMMITTED:
  duraid
  jeffc
  lattner

CHANGED FILES:
  llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/include/llvm/Target/TargetInstrInfo.h
  llvm/lib/CodeGen/ELFWriter.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.h
  llvm/lib/Target/Alpha/AlphaRegisterInfo.td
  llvm/lib/Target/IA64/IA64ISelPattern.cpp
  llvm/lib/Target/IA64/IA64RegisterInfo.cpp
  llvm/lib/Target/IA64/IA64RegisterInfo.h
  llvm/lib/Target/IA64/IA64RegisterInfo.td
  llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPC32RegisterInfo.h
  llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
  llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
  llvm/lib/Target/Skeleton/SkeletonRegisterInfo.cpp
  llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h
  llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td
  llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
  llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
  llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
  llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
  llvm/lib/Target/Target.td
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.h
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/utils/TableGen/CodeGenInstruction.h
  llvm/utils/TableGen/CodeGenRegisters.h
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/InstrInfoEmitter.cpp
  llvm/utils/TableGen/InstrInfoEmitter.h
  llvm/utils/TableGen/Record.cpp
  llvm/utils/TableGen/Record.h
  llvm/utils/TableGen/RegisterInfoEmitter.cpp
  llvm/win32/x86/x86.vcproj