[llvm-dev] Defining instruction aliases

[Craig Topper via llvm-dev]

Can you clarify what you mean by "different kinds of immediates"? Are you
talking about a fixed immediate like "1" or an immediate that requires a
predicate to check the value?

~Craig


On Mon, Jan 17, 2022 at 11:10 AM David Greene via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hey everyone,
>
>
>
> We've defined some instruction aliases for our target but are having
>
> trouble with the assembler.  According to the documentation
>
> (https://llvm.org/docs/CodeGenerator.html#instruction-aliases) LLVM has
>
> the capability of defining aliases with different kinds of operands.  We
>
> use that capability to define, for example, different alises based on
>
> the kind of immediate seen.
>
>
>
> However, it seems that the generated assembler can't distinguish these
>
> different kinds of immediates and ends up encoding the wrong operation,
>
> leading to incorrect assembly.
>
>
>
> Is this a known limitation?  Are we perhaps missing some option to the
>
> InstAlias class (UseInstAsmMatchConverter?), some option to TableGen or
>
> perhaps we can add some custom code to pick the right MC instruction?
>
>
>
> I'm thinking AsmMatchConverter might be what we need but a quick search
>
> didn't locate any documentation of what this is and how to use it.
>
>
>
> Thanks in advance for the help!
>
>
>
> David
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