[llvm-dev] AArch64 global isel

[Adrian Tong via llvm-dev]

It worked. I've spent quite some time debugging this.

Thank you!


On Tue, Jan 11, 2022 at 4:44 PM Jason Eckhardt <jeckhardt at nvidia.com> wrote:

> One problem is that the predicate in your PatFrag is defined in terms of
> SDNode, which won't work for GISel. Try adding a GISelPredicateCode to do
> the equivalent test on Machine IR. See also
> https://llvm.org/docs/GlobalISel/InstructionSelect.html (especially
> regarding SD imports).
>
> ------------------------------
> *From:* llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Adrian
> Tong via llvm-dev <llvm-dev at lists.llvm.org>
> *Sent:* Monday, January 10, 2022 11:33 PM
> *To:* LLVM Developers Mailing List <llvm-dev at lists.llvm.org>
> *Subject:* [llvm-dev] AArch64 global isel
>
> *External email: Use caution opening links or attachments*
> Hi
> I am writing a pattern to select ushr+or into usra on AArch64. I changed
> the following pattern from add to add_and_or_is_add. One test
> case test/CodeGen/AArch64/GlobalISel/combine-udiv.ll that uses global isel
> starts to fail and what was selected into usra is now selected into
> ushr+add. This only happens in global isel, how can i debug this ?
>
> 6471 defm USRA     : SIMDScalarRShiftDTied<   1, 0b00010, "usra",
> 6472     TriOpFrag<(add_and_or_is_add /* changed from add */ node:$LHS,
> 6473                    (AArch64vlshr node:$MHS, node:$RHS))>>;
>
> 6345 // Match add node and also treat an 'or' node is as an 'add' if the
> or'ed operands
> 6346 // have no common bits.
> 6347 def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
> 6348                          [(add node:$lhs, node:$rhs), (or node:$lhs,
> node:$rhs)],[{
> 6349    if (N->getOpcode() == ISD::ADD)
> 6350      return true;
> 6351    return CurDAG->haveNoCommonBitsSet(N->getOperand(0),
> N->getOperand(1));
> 6352 }]>;
>
> Thanks
> -Adrian
>
>
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