[llvm-dev] [RFC] Eliminating non-IR floating-point controls in the selection DAG
Renato Golin via llvm-dev
llvm-dev at lists.llvm.org
Fri Oct 29 03:00:25 PDT 2021
IIRC, the fp-contract change was to fix some broken code but not break
more. Copying Sebastian who was working on that at that time.
I agree we shouldn't have overriding behaviour flags in the back-end if the
IR explicitly says what it wants. But I'd be cautious as to move all such
flags to instructions.
First, this would be a behavioural change that needs the IR to change, so
would affect every LLVM IR front-end, which makes it a pervasive change
throughout the downstream users. So, if we decide we want to do this, we
need to replace the current mess with a consistent implementation that wont
break everybody else's.
Second, module/function flags can control fine-grain behaviour without
bloating the IR. I don't know how the instruction flag changes the binary
representation, it's probably very small anyway, but so are the
module/function ones, so overall, a definite increase in size.
Finally, I think we need to separate the IR from DAG/MIR behaviour. It
seems to me that the target option is what overrides the behaviour, not
function/module options, so we should worry about the targets' behaviour,
not at which level the flag is set.
There's a perfectly valid solution that has module/function/instruction
flags controlling behaviour, with the most specific overriding the least
specific, and none of that overridden by the target. This means we can
still use the same IR flags in the same way (thus not forcing all
front-ends to change) and still correct the behaviour by not making the
target ignore all that.
Does any of that make any sense?
On Fri, 29 Oct 2021 at 01:22, Kaylor, Andrew via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi everyone,
> This is related to the recent thread about fp-contract and front end
> pragma controls, but I want to generalize the discussion in terms of how
> the target-independent codegen in the backend is implemented.
> Until sometime in 2017 (I think) the fast-math flags were not passed
> through to the Selection DAG, and so the only ways to control
> floating-point behavior were through settings in the TargetOptions or by
> settings function attributes. Since 2017, however, the fast-math flags have
> been attached to floating-point nodes in the selection DAG. This leads to
> some ambiguous situations where the TargetOptions or function attributes
> can override the absence of fast-math flags on individual nodes. An example
> of this is the fp-contract setting. If a source file is compiled with clang
> using the ‘-ffp-contract=fast’ setting but the file contains either
> “#pragma STDC FP_CONTRACT OFF” or “#pragma clang fp contract(off)” the
> front end will generate IR without the ‘contract’ fast-math flag set, but
> the X86 backend will generate an FMA instruction anyway.
> This is particularly bad in the case of CUDA, because CUDA uses
> fp-contract=fast by default. So, the user’s code can explicitly say “don’t
> generate fma here” and the compiler will respond, “meh, I think I will
> There are other cases where the backend code will check for
> TargetOption::UnsafeFPMath for things like reassociation that can be
> represented using fast-math flags.
> That brings me to the RFC part of my message. I’d like to start updating
> the backend so that it doesn’t do things like this. As a general principle,
> I would say, “All semantics must be represented in the IR and the backend
> must respect the IR semantics.” And a corollary: “Anything which can be
> represented at the instruction level must be represented at the instruction
> level.” This corollary would eliminate potential conflicts between function
> attributes (like "unsafe-fp-math") and individual IR instructions.
> As a first step toward this goal, I’ve prepared a patch which closes the
> back door for fp-contract control.
> This patch is currently incomplete, in as much as I didn’t update failing
> tests for several target architectures. I did update the X86 and AMDGPU
> tests to provide examples of how they can be made to work. I will fix the
> rest if we decide this is the correct direction. There is a failing CUDA
> test in the clang front end that I think will require a different approach
> involving some driver changes to get clang to generate IR for the semantics
> it intends rather than setting an option and counting on the backend to
> disregard the IR.
> Thanks in advance for any feedback!
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
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