[llvm-dev] Need a help with CodeGen's td files
Serguei Katkov via llvm-dev
llvm-dev at lists.llvm.org
Mon Oct 11 22:58:20 PDT 2021
I need a help/advice how to go with the following problem.
There are two independently created patches https://reviews.llvm.org/D111114 and https://reviews.llvm.org/D107301 which actually handle the same problem.
There is pseudo instruction STATEPOINT and it is platform-independent.
However the list of implicit-defs is different on different platforms. Specifically on aarch64 it has implicit def of link register.
I failed to find a way how to override the list of implicit defs of pseudo instruction for some specific platform.
So I wonder
1. whether it is possible?
2. How and how difficult will be to extend td files support to allow this overriding if it is not possible?
3. Does it make sense to extend the support complicating things or it is better to go with workaround implemented in patches above?
Thanks in advance,
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