[llvm-dev] Question about LLVM backend and TableGen

[Madhur Amilkanthwar via llvm-dev]

A record in a tablegen file has no meaning unless there is a backend which
processes it. A record gets processed by one or more tablegen backends and
the backend extracts what it wants.

There are several backends to tablegen and you can find more details here  -
https://llvm.org/docs/TableGen/BackEnds.html#llvm-backends.



On Mon, Nov 22, 2021 at 6:53 PM Nemanja Ivanovic via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> First off, not a dumb question at all. Most tools in the LLVM tree have
> reasonably good debug output so you usually don't have to hack the tool to
> see what it's doing. For llvm-tblgen for example, a very useful option is
> --print-detailed-records which will show you what it is consuming and the
> records it creates.
> If you only care to see what code llvm-tblgen produces from the .td files,
> you can find the outputs in the build directory. They are (roughly
> speaking) named for the target and the type of output llvm-tblgen was asked
> to produce. For example:
>
> $ grep -l BEQ $LLVM_BUILD/lib/Target/RISCV/RISCVGen*
> $LLVM_BUILD/lib/Target/RISCV/RISCVGenAsmMatcher.inc
> $LLVM_BUILD/lib/Target/RISCV/RISCVGenAsmWriter.inc
> $LLVM_BUILD/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc
> $LLVM_BUILD/lib/Target/RISCV/RISCVGenDAGISel.inc
> $LLVM_BUILD/lib/Target/RISCV/RISCVGenDisassemblerTables.inc
> $LLVM_BUILD/lib/Target/RISCV/RISCVGenInstrInfo.inc
> $LLVM_BUILD/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc
>
> So you can see all the different things that llvm-tblgen produces for that
> record (i.e. assembly/disassembly info, ISEL info, etc.).
> P.S. You can also see all the options that llvm-tblgen has (or pretty much
> any tool) by invoking the tool with --help.
>
>
> On Sat, Nov 20, 2021 at 8:17 AM Sheng Yan Chen via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi all,
>>
>> I'm hacking LLVM TableGen file and I'm stuck with that. My problem is: I
>> know what the records mean, but I don't know what it will become.
>>
>> Here's a simple example from RISCVInstrInfo.td
>>
>> def BEQ   :  BranchCC_rri<0b000, "beq">
>>
>> I know it is a branch-if-equal instruction in RISCV, I know "0b000" is
>> its encoding, I know "beq" is its assembly name. But I don't know what it
>> will becomes after TableGen processing it.
>>
>> Will it be used at Instruction pattern matching ? Will it be used at
>> disassembler ? Will it be used at assembler ?
>>
>> How can I know what this record will become after TableGen processing it ?
>>
>> Thinking from another way, when I writing a new backend, how can I know
>> what kinds of TableGen record I need to supply ?
>>
>> Is hacking TableGen backend a good way to get through this ?
>>
>> Thanks for reading this dumb question :)
>>
>> Sheng.
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
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-- 
*Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this
mail are of my own and my employer has no take in it. *
Thank You.
Madhur D. Amilkanthwar
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