[llvm-dev] LLVM with RISC-V V-extension intrinsic support

[Kai Wang via llvm-dev]

Hi,

We would like to announce that the RISC-V V-extension v0.10 has been
implemented in LLVM and the work has been committed upstream.


Barcelona Supercomputing Center (BSC), Codeplay Software, and SiFive have
worked together to implement the RVV C API intrinsics for the V-extension
and have implemented the foundation of CodeGen for Vector Length Specific
(VLS) and Vector Length Agnostic (VLA) autovectorization for RISC-V.


What we have committed to LLVM upstream:

* Support for the v0.10 V-extension specification

* Support for the RVV C intrinsics in
https://github.com/riscv/rvv-intrinsic-doc/tree/v0.10

* Implement the draft vector calling convention in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171


Known issues:

* C intrinsics for Zvlsseg implementation is under discussion:

 - https://lists.llvm.org/pipermail/llvm-dev/2021-March/149518.html

* What type we should use for fp16 is under discussion:

 -
https://github.com/riscv/rvv-intrinsic-doc/issues/18#issuecomment-818472454


RISC-V RVV example:

https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_saxpy.c


Build command:

clang --target=riscv64-unknown-elf -march=rv64gcv0p10
-menable-experimental-extensions rvv_saxpy.c -o rvv_saxpy.elf
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