[llvm-dev] LLVM with RISC-V V-extension intrinsic support

Kai Wang via llvm-dev llvm-dev at lists.llvm.org
Fri May 14 02:30:24 PDT 2021


We would like to announce that the RISC-V V-extension v0.10 has been
implemented in LLVM and the work has been committed upstream.

Barcelona Supercomputing Center (BSC), Codeplay Software, and SiFive have
worked together to implement the RVV C API intrinsics for the V-extension
and have implemented the foundation of CodeGen for Vector Length Specific
(VLS) and Vector Length Agnostic (VLA) autovectorization for RISC-V.

What we have committed to LLVM upstream:

* Support for the v0.10 V-extension specification

* Support for the RVV C intrinsics in

* Implement the draft vector calling convention in

Known issues:

* C intrinsics for Zvlsseg implementation is under discussion:

 - https://lists.llvm.org/pipermail/llvm-dev/2021-March/149518.html

* What type we should use for fp16 is under discussion:


RISC-V RVV example:


Build command:

clang --target=riscv64-unknown-elf -march=rv64gcv0p10
-menable-experimental-extensions rvv_saxpy.c -o rvv_saxpy.elf
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20210514/5fbdee44/attachment-0001.html>

More information about the llvm-dev mailing list