[llvm-dev] [RISCV] Does "V" Extention come with "F" "D" "Zfh" Extentions?

[Craig Topper via llvm-dev]

We need to add a TTI interface and vectorizer changes for it to know which
element types are legal to make scalable vectors for. AArch64 has a similar
problem with at least __int128. https://godbolt.org/z/r38c1Mdfv

~Craig


On Mon, Mar 29, 2021 at 6:32 AM Kai Wang via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hi,
>
> There is no such implication between V and F/D/Zfh. If you want to use the
> vector unit to process float/double/fp16 data, you need to specify F, D and
> Zfh accordingly.
>
> Kai
>
> On Mon, Mar 29, 2021 at 5:58 PM DriveLife via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi all,
>> When I tried to run "opt -loop-vectorize" on a testcase, an "UNREACHABLE
>> executed" error was received.
>> The full command is "./build/bin/opt -loop-vectorize -dce -instcombine
>> -mtriple riscv64-linux-gnu -mattr=+experimental-v
>> -debug-only=loop-vectorize -S
>> llvm/test/Transforms/LoopVectorize/RISCV/basic-vec.ll"(basic-vec.ll as
>> attachment).
>> Missing "+f" in "-mattr" is the reason of "UNREACHABLE executed" error.
>> The command "./build/bin/opt -loop-vectorize -dce -instcombine -mtriple
>> riscv64-linux-gnu -mattr=+experimental-v,+f -debug-only=loop-vectorize -S
>> llvm/test/Transforms/LoopVectorize/RISCV/basic-vec.ll" works well.
>> So can we assume that if a target has StdExtF, it also has StdExtF,
>> StdExtD and StdExtZfh?
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