[llvm-dev] Register constraints for implicit register usage

[David Callahan via llvm-dev]

I am working on a machine with a special register class which here I will call  Xrc containing registers X0..Xk.
Some instructions implicitly reference X0. I am modeling this with a pseudo instruction that makes that reference explicit and created a register class X0rc which just contains X0.  This seems to work fine and SelectionDAG introduces copies between the two register classes where I would expect them.
The problem I face is that MachineCSE::PerformTrivialCopyPropagation eliminates these copies and effectively changes the register class for the output register of unconstrained instructions to be X0rc. This is done so aggressively that I end up with multiple overlapping live ranges and so values are constantly being spilled and reloaded. Also, it creates situations where multiple operands of an instruction are bound to this class and so register allocation fails.
What is the preferred way to handle this kind of situation?
Thanks
david

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