[llvm-dev] isHardwareLoopProfitable() called with empty assumption cache in hwloops pass

[Sjoerd Meijer via llvm-dev]

I can't imagine that being the intended behaviour. I don't think we have paid much attention to the assumption cache in the ARM implementation. Some parts of the hardware loop infrastructure were factored out from the initial PPC implementation, which I think explains it is there and used by PPC, but not in the ARM implementation. But perhaps Sam knows more.

I have never looked into the AssumptionCache, but I assume there's way to retrigger and repopulate it (after CGP)?

Just out of curiousity, can you perhaps tell more how you would like to persuade/force hardware loops with an assume? There are some options at the moment (but would apply to all loops in the compilation unit), don't think we e.g. looked into a pragma, so it sounds interesting. I guess this is a hint about the iteration count?

Cheers,
Sjoerd.
________________________________
From: Janek Van Oirschot <janekvo at graphcore.ai>
Sent: 24 March 2021 17:27
To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
Cc: Sam Parker <Sam.Parker at arm.com>; Sjoerd Meijer <Sjoerd.Meijer at arm.com>; David Green <David.Green at arm.com>
Subject: isHardwareLoopProfitable() called with empty assumption cache in hwloops pass


Hey all,



It seems that when HardwareLoops calls the isHardwareLoopProfitable TTI hook, it never has a populated AssumptionCache. Some debugging revealed that HardwareLoops runs during the PreISel phase for ARM and PPC. However, the CodeGenPrepare pass runs before PreISel and removes all assumes meaning that the AssumptionCache in HardwareLoops will end up empty.



>From what I gather (and let me know if I'm wrong), only PPC uses the AssumptionCache in isHardwareLoopProfitable but only to aid in some cost analysis. I was wondering whether it's intended behaviour to have an empty AssumptionCache during HardwareLoops? I ask because I was looking into using assumes to persuade HardwareLoops into emitting hardware intrinsics for our (downstream) target.



Kind regards,

Janek van Oirschot




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