[llvm-dev] LLVM Weekly - #376, March 15th 2021

Mon Mar 15 11:45:05 PDT 2021

LLVM Weekly - #376, March 15th 2021
===================================

If you prefer, you can read a HTML version of this email at
<http://llvmweekly.org/issue/376>.

Welcome to the three hundred and seventy-sixth issue of LLVM Weekly, a weekly
newsletter (published every Monday) covering developments in LLVM, Clang, and
related projects. LLVM Weekly is brought to you by [Alex
Bradbury](https://www.linkedin.com/in/alex-bradbury/). Subscribe to future
issues at <http://llvmweekly.org> and pass it on to anyone else you think may
be interested. Please send any tips or feedback to <asb at asbradbury.org>, or
@llvmweekly or @asbradbury on Twitter.

## News and articles from around the web

LLVM was accepted as a mentor organisation in [Google Summer of Code
2021](https://summerofcode.withgoogle.com/). Find out more about suggested
projects [here](https://llvm.org/OpenProjects.html#gsoc21).

Xilinx have [open-sourced their LLVM-based Vitis high level synthesis
frontend](https://www.eetimes.com/xilinx-opens-up-vitis-hls-tool-for-fpgas/).
The code is available [on GitHub](https://github.com/Xilinx/HLS).

Asher Mancinelli has blogged about [parameterizing GTest by both value and
type](https://ashermancinelli.github.io/gtest-type-val-param), using recent
work to do this for Flang as an example.

## On the mailing lists

* Andrei Safronov [proposed the Tensilica Xtensa backend for
  upstreaming](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149090.html).
  This backend has been written by Espressif Systems.

* Rafael Auler [shared an update on rebasing BOLT and plans for upstreaming
  it](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149135.html). Chris
  Lattner [posted some
  thoughts](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149168.html)
  on how BOLT could be added to the project (suggesting to start with a
  `bolt/` top-level directory) and noted that LLVM might benefit from more
  code moving to top-level directories, e.g. Support/ADT and perhaps the MC
  layer.

* Pavel Labath [proposed removing Linux Mips support from
  LLDB](https://lists.llvm.org/pipermail/lldb-dev/2021-March/016777.html) on
  the basis that it's untested and unmaintained.

* Vaibhav Yenamandra posted an RFC on [extending Clang's `-fdiagnostic-format`
  to emit machine-readable
  diagnostics](https://lists.llvm.org/pipermail/cfe-dev/2021-March/067907.html),
  and proposes using the [standardised SARIF
  format](https://docs.oasis-open.org/sarif/sarif/v2.1.0/sarif-v2.1.0.html).

* Konrad Trifunovic posted a [summary of the discussion so far on upstreaming
  a SPIR-V
  backend](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149175.html).

* LLVM 12.0.0-rc3 [has been
  tagged](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149102.html).

* In response to query about a proposed GSoC project on distributed lit
  testing, Sam McCall [described a system used at Google involving a custom
  runner and distributed build
  system](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149178.html).

* Serge Pavlov shared an RFC on [supporting non-default floating point
  environments on
  RISC-V](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149177.html).

## LLVM commits

* The M68k backend was committed.
  [5033431](https://reviews.llvm.org/rG503343191e12),
  [bec7b16](https://reviews.llvm.org/rGbec7b166923b),
  [8dddc15](https://reviews.llvm.org/rG8dddc15297f1),
  [5ac19e0](https://reviews.llvm.org/rG5ac19e0acf86), and more.

* Documentation was added for building a Windows Itanium toolchain.
  [c5c6f18](https://reviews.llvm.org/rGc5c6f187a32d).

* An llvm.experimental.vector.splice intrinsic was added.
  [2750f3ed](https://reviews.llvm.org/rG2750f3ed3155).

* Code comments were added to the Arm backend explaining the stack frame
  layout. [8d632ca](https://reviews.llvm.org/rG8d632ca43655).

* `-Werror=return=type` is now set by default when building LLVM.
  [ce94a16](https://reviews.llvm.org/rGce94a161651d).

* Support was added for handling i64 arguments to RISC-V vector intrinsics on
  RV32. [0c73a50](https://reviews.llvm.org/rG0c73a506e809).

* Support for lowering to WLS (While Loop Start) on Arm targets with low
  overhead loops was improved.
  [fad70c3](https://reviews.llvm.org/rGfad70c306854).

* The frame layout for RISC-V vectors was updated.
  [a9b9c64](https://reviews.llvm.org/rGa9b9c64fd4c8).

* Support was added for generating `DBG_VALUE_LIST` and processing it in
  LiveDebugValues. [5491a86](https://reviews.llvm.org/rG5491a86f59ce),
  [e2196dd](https://reviews.llvm.org/rGe2196ddcdbf1).

## Clang commits

* Initial M68k was committed in Clang.
  [5eb7a58](https://reviews.llvm.org/rG5eb7a5814a5c),
  [5509748](https://reviews.llvm.org/rG5509748f2ce5).

* Clang gained a new warning for when a function argument is less aligned than
  a parameter. [7e5cea5](https://reviews.llvm.org/rG7e5cea5b509f).

* A custom TableGen backend was added for RISC-V vector intrinsics.
  [d6a0560](https://reviews.llvm.org/rGd6a0560bf258).

## Other project commits

* MLIR gained a data layout modeling subsystem, allowing size and alignment
  properties of a type to be queried.
  [3ba14fa](https://reviews.llvm.org/rG3ba14fa0ce46).

* The first set of flang tests have been ported to gtest.
  [95193ac](https://reviews.llvm.org/rG95193ac5ba60).

* The scudo allocator now supports memory tagging in the secondary allocator.
  [3f71ce8](https://reviews.llvm.org/rG3f71ce85897c).

* A CMake option was added to build LLVM's libc standalone, without mixing
  with another libc (for testing - LLVM's libc isn't yet complete enough to
  use this mode as standard).
  [e9e788d](https://reviews.llvm.org/rGe9e788d145f5).

* The std::movable, std::copyable, std::semiregular, and std::regular concepts
  were added to libcxx. [dc9f385](https://reviews.llvm.org/rGdc9f38572224),
  [8ef69c6](https://reviews.llvm.org/rG8ef69c66d5aa),
  [1543955](https://reviews.llvm.org/rG154395536e3c),
  [8d4af1b](https://reviews.llvm.org/rG8d4af1b6e033).