[llvm-dev] llvm-mca for in-order CPUs (was Re: LLVM Weekly - #375, March 8th 2021)

[Jay Foad via llvm-dev]

On Tue, 9 Mar 2021 at 17:54, Andrew Trick <atrick at apple.com> wrote:
> We should really have some alias for MicroOpBufferSize=0/1. It’s too cryptic.
>
> InOrder => MicroOpBufferSize=1
> VLIW => MicroOpBufferSize=0
>
> It only affects what instructions the scheduler puts in the ready queue. In VLIW-mode, the scheduler only considers instructions that can be scheduled in the current group. In InOrder mode, the scheduler can weigh the potential latency stall against other heuristics. I don’t think it’s relevant for MCA.

Thanks. I found there is already an MCSchedModel::isOutOfOrder which
makes it slightly less cryptic. I've put a patch up at
https://reviews.llvm.org/D98356 to try to support MicroOpBufferSize=1
in llvm-mca as simply as possible.

Jay.