[llvm-dev] Problems with subreg-liveness and Greedy RA

Nemanja Ivanovic via llvm-dev llvm-dev at lists.llvm.org
Wed Jun 23 12:18:17 PDT 2021


Sorry, it would appear that the dev list stripped my attachment. I have
reduced the file using bugpoint and produced the output from that.
Attaching it here.

Nemanja

On Wed, Jun 23, 2021 at 2:23 PM Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
wrote:

> Thank you so much for taking the time to answer Quentin.
>
> The bad copies are definitely added by live range splitting. The issue
> seems to be the LaneBitmasks for the various subregisters. Honestly, I
> don't really know what the bits of LaneBitmask produced by TblGen are meant
> to mean, but I can't make any sense of them. And those seem to lead the
> register allocator astray.
> Here are the LaneBitmasks from the register include file:
> static const LaneBitmask SubRegIndexLaneMaskTable[] = {
>   LaneBitmask::getAll(),
>   LaneBitmask(0x0000000000000001), // sub_32
>   LaneBitmask(0x0000000000000002), // sub_64
>   LaneBitmask(0x0000000000000004), // sub_eq
>   LaneBitmask(0x0000000000000001), // sub_gp8_x0
>   LaneBitmask(0x0000000000000200), // sub_gp8_x1
>   LaneBitmask(0x0000000000000008), // sub_gt
>   LaneBitmask(0x0000000000000010), // sub_lt
>   LaneBitmask(0x0000000000000042), // sub_pair0
>   LaneBitmask(0x0000000000000180), // sub_pair1
>   LaneBitmask(0x0000000000000020), // sub_un
>   LaneBitmask(0x0000000000000002), // sub_vsx0
>   LaneBitmask(0x0000000000000040), // sub_vsx1
>   LaneBitmask(0x0000000000000040), // sub_vsx1_then_sub_64
>   LaneBitmask(0x0000000000000080), // sub_pair1_then_sub_64
>   LaneBitmask(0x0000000000000080), // sub_pair1_then_sub_vsx0
>   LaneBitmask(0x0000000000000100), // sub_pair1_then_sub_vsx1
>   LaneBitmask(0x0000000000000100), // sub_pair1_then_sub_vsx1_then_sub_64
>   LaneBitmask(0x0000000000000200), // sub_gp8_x1_then_sub_32
>  };
>
> For example, what does it mean that the mask for sub_64 and sub_vsx0 are
> the same? The two subregisters certainly do not represent the same lanes in
> their respective registers. The sub_vsx0 subregister is the first VSX
> register in a VSX register pair. And each of the two subregisters of a VSX
> register pair (sub_vsx0, sub_vsx1) have their own scalar subregister (
> sub_64).
>
> I have also attached the output of RA, but it is huge :(
> It is the result of specifying options -debug-only=regalloc
> -print-before=greedy -print-after=greedy on the command line.
>
> On Tue, Jun 22, 2021 at 3:21 PM Quentin Colombet <qcolombet at apple.com>
> wrote:
>
>>
>>
>> On Jun 21, 2021, at 10:05 AM, Nemanja Ivanovic via llvm-dev <
>> llvm-dev at lists.llvm.org> wrote:
>>
>> I am having a really difficult time with subregister related issues when
>> I turn
>> on subregister liveness tracking.
>>
>> Before RA:
>> 79760B    %2216:vsrc = LXVDSX %5551:g8rc_and_g8rc_nox0, %2215:g8rc ::
>> (load 8 from %ir.scevgep1857.cast, !alias.scope !92, !noalias !93)
>> 79872B    %2225:vsrprc = LXVP 352, %661:g8rc_and_g8rc_nox0
>> 84328B    %5540:vsrc = contract nofpexcept XVMADDADP %5540:vsrc(tied-def
>> 0), %2225.sub_vsx0:vsrprc, %2216:vsrc, implicit $rm
>>
>> After RA (greedy):
>> 79744B    %2214:vsrc = LXVDSX %5551:g8rc_and_g8rc_nox0, %6477:g8rc ::
>> (load 8 from %ir.scevgep1860.cast, !alias.scope !92, !noalias !93)
>> 79872B    %7503:vsrprc = LXVP 352, %661:g8rc_and_g8rc_nox0
>> 80248B    %7527:vsrprc = COPY %7503:vsrprc
>> 80988B    undef %7526.sub_64:vsrprc = COPY %7527.sub_64:vsrprc
>> 84324B    undef %7501.sub_64:vsrprc = COPY %7526.sub_64:vsrprc
>> 84328B    %5546:vsrc = contract nofpexcept XVMADDADP %5546:vsrc(tied-def
>> 0), %7501.sub_vsx0:vsrprc, %2214:vsrc, implicit $rm
>>
>> Subregister definitions for PPC:
>> def sub_64 : SubRegIndex<64>;
>> def sub_vsx0 : SubRegIndex<128>;
>> def sub_vsx1 : SubRegIndex<128, 128>;
>> def sub_pair0 : SubRegIndex<256>;
>> def sub_pair1 : SubRegIndex<256, 256>;
>>
>> So the instruction at 84328B uses the full register %2216 and the high
>> order
>> 128 bits of (256-bit) register %2225. However, the register allocator
>> splits
>> the live range and introduces a copy of the high order 64 bits of that
>> 256-bit
>> register, then another copy of that copy and rewrites the use in
>> instruction
>> 84328B to that copy. The copy is marked undef so the register allocator
>> assigns just some random register to the use of that copy in 84328B.
>>
>> Or maybe I am completely misinterpreting the meaning of the debug dumps
>> from the register allocator.
>>
>> This appears to be related to lane masks and dead lane detection although
>> I don't see dead lane detection marking anything unexpected as undef
>> (seems
>> to just be INSERT_SUBREG and PHI).
>>
>>
>> Are the copies added by dead lane detection or by live-range splitting?
>>
>> The undef flag on the definition of %7501 is suspicious and depending on
>> how you look at it, so is the one on %7526. Essentially, we are losing the
>> full copy in this chain of copies and I wonder what is at fault here.
>>
>> Could you share the debug output of regalloc?
>>
>>
>> If anyone has suggestions on what might be the issue and/or how to go
>> about figuring this out and fixing it, I would really appreciate it.
>>
>> Nemanja
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>>
>>
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Computing live-in reg-units in ABI blocks.
0B	%bb.0 R3#0 R4#0
Created 2 new intervals.
********** INTERVALS **********
R3 [0B,32r:0)  0 at 0B-phi
R4 [0B,16r:0)  0 at 0B-phi
%1 [288r,3968B:0)  0 at 288r weight:0.000000e+00
%5 [400r,3968B:0)  0 at 400r weight:0.000000e+00
%6 [432r,3968B:0)  0 at 432r weight:0.000000e+00
%8 [448r,1120B:0)  0 at 448r weight:0.000000e+00
%9 [1136r,3920r:0)  0 at 1136r weight:0.000000e+00
%10 [1152r,3904r:0)  0 at 1152r weight:0.000000e+00
%11 [1168r,1264r:0)  0 at 1168r weight:0.000000e+00
%12 [1184r,1296r:0)  0 at 1184r weight:0.000000e+00
%13 [1200r,1280r:0)  0 at 1200r weight:0.000000e+00
%14 [1216r,1264r:0)  0 at 1216r weight:0.000000e+00
%15 [1232r,3728r:0)  0 at 1232r weight:0.000000e+00
%16 [1248r,3968B:0)  0 at 1248r weight:0.000000e+00
%17 [3712r,3968B:0)  0 at 3712r weight:0.000000e+00
%18 [3856r,3968B:0)  0 at 3856r weight:0.000000e+00
%19 [3872r,3968B:0)  0 at 3872r weight:0.000000e+00
%20 [3888r,3968B:0)  0 at 3888r weight:0.000000e+00
%21 [3904r,3968B:0)  0 at 3904r weight:0.000000e+00
%22 [3920r,3968B:0)  0 at 3920r weight:0.000000e+00
%24 [32r,3968B:0)  0 at 32r weight:0.000000e+00
%25 [16r,448r:0)  0 at 16r weight:0.000000e+00
%27 [48r,64r:0)  0 at 48r weight:0.000000e+00
%28 [272r,1120B:0)  0 at 272r weight:0.000000e+00
%29 [544r,1120B:0)  0 at 544r weight:0.000000e+00
%30 [528r,1120B:0)  0 at 528r weight:0.000000e+00
%31 [560r,1120B:0)  0 at 560r weight:0.000000e+00
%32 [112r,128r:0)  0 at 112r weight:0.000000e+00
%33 [128r,144r:0)  0 at 128r weight:0.000000e+00
%34 [144r,208r:0)  0 at 144r L0000000000000040 [144r,160r:0)  0 at 144r L0000000000000002 [144r,208r:0)  0 at 144r weight:0.000000e+00
%35 [160r,192r:0)  0 at 160r weight:0.000000e+00
%36 [192r,224r:0)  0 at 192r weight:0.000000e+00
%37 [176r,192r:0)  0 at 176r weight:0.000000e+00
%38 [208r,224r:0)  0 at 208r weight:0.000000e+00
%39 [224r,240r:0)  0 at 224r L0000000000000002 [224r,240r:0)  0 at 224r L0000000000000040 [224r,224d:0)  0 at 224r weight:0.000000e+00
%40 [240r,256r:0)  0 at 240r weight:0.000000e+00
%41 [256r,3968B:0)  0 at 256r weight:0.000000e+00
%42 [304r,336r:0)  0 at 304r L0000000000000002 [304r,320r:0)  0 at 304r L0000000000000040 [304r,336r:0)  0 at 304r weight:0.000000e+00
%43 [320r,368r:0)  0 at 320r weight:0.000000e+00
%44 [336r,352r:0)  0 at 336r weight:0.000000e+00
%45 [352r,3968B:0)  0 at 352r weight:0.000000e+00
%46 [368r,3968B:0)  0 at 368r weight:0.000000e+00
%47 [384r,400r:0)  0 at 384r weight:0.000000e+00
%48 [416r,432r:0)  0 at 416r weight:0.000000e+00
%49 [464r,480r:0)  0 at 464r weight:0.000000e+00
%50 [496r,3968B:0)  0 at 496r weight:0.000000e+00
%51 [512r,560r:0)  0 at 512r weight:0.000000e+00
%54 [1264r,1312r:0)  0 at 1264r weight:0.000000e+00
%55 [1280r,1328r:0)  0 at 1280r weight:0.000000e+00
%56 [1296r,1344r:0)  0 at 1296r weight:0.000000e+00
%57 [1312r,1440r:0)  0 at 1312r weight:0.000000e+00
%58 [1328r,1456r:0)  0 at 1328r weight:0.000000e+00
%59 [1344r,1472r:0)  0 at 1344r weight:0.000000e+00
%60 [1360r,3760r:0)  0 at 1360r weight:0.000000e+00
%61 [576r,3968B:0)  0 at 576r weight:0.000000e+00
%62 [1376r,1504r:0)  0 at 1376r weight:0.000000e+00
%63 [592r,3968B:0)  0 at 592r weight:0.000000e+00
%64 [1392r,1552r:0)  0 at 1392r weight:0.000000e+00
%65 [608r,3968B:0)  0 at 608r weight:0.000000e+00
%66 [1408r,1424r:0)  0 at 1408r L0000000000000040 [1408r,1424r:0)  0 at 1408r L0000000000000002 [1408r,1408d:0)  0 at 1408r weight:0.000000e+00
%67 [1424r,1472r:0)  0 at 1424r weight:0.000000e+00
%68 [1440r,1488r:0)  0 at 1440r weight:0.000000e+00
%70 [1456r,1504r:0)  0 at 1456r weight:0.000000e+00
%71 [1472r,1520r:0)  0 at 1472r weight:0.000000e+00
%72 [1488r,1536r:0)  0 at 1488r weight:0.000000e+00
%73 [1504r,1552r:0)  0 at 1504r weight:0.000000e+00
%74 [1520r,1568r:0)  0 at 1520r weight:0.000000e+00
%75 [1536r,1584r:0)  0 at 1536r weight:0.000000e+00
%76 [1552r,1600r:0)  0 at 1552r weight:0.000000e+00
%77 [1568r,1616r:0)  0 at 1568r weight:0.000000e+00
%78 [1584r,1632r:0)  0 at 1584r weight:0.000000e+00
%79 [1600r,1648r:0)  0 at 1600r weight:0.000000e+00
%80 [1616r,1664r:0)  0 at 1616r weight:0.000000e+00
%81 [1632r,1680r:0)  0 at 1632r weight:0.000000e+00
%82 [1648r,1696r:0)  0 at 1648r weight:0.000000e+00
%83 [1664r,1712r:0)  0 at 1664r weight:0.000000e+00
%84 [1680r,1744r:0)  0 at 1680r weight:0.000000e+00
%85 [1696r,1760r:0)  0 at 1696r weight:0.000000e+00
%86 [1712r,1776r:0)  0 at 1712r weight:0.000000e+00
%87 [624r,3968B:0)  0 at 624r weight:0.000000e+00
%88 [1728r,1840r:0)  0 at 1728r weight:0.000000e+00
%89 [1744r,1792r:0)  0 at 1744r weight:0.000000e+00
%90 [1760r,1808r:0)  0 at 1760r weight:0.000000e+00
%91 [1776r,1824r:0)  0 at 1776r weight:0.000000e+00
%92 [1792r,1840r:0)  0 at 1792r weight:0.000000e+00
%93 [1808r,1856r:0)  0 at 1808r weight:0.000000e+00
%94 [1824r,1872r:0)  0 at 1824r weight:0.000000e+00
%95 [1840r,1888r:0)  0 at 1840r weight:0.000000e+00
%96 [1856r,1904r:0)  0 at 1856r weight:0.000000e+00
%97 [1872r,1920r:0)  0 at 1872r weight:0.000000e+00
%98 [1888r,1936r:0)  0 at 1888r weight:0.000000e+00
%99 [1904r,1952r:0)  0 at 1904r weight:0.000000e+00
%100 [1920r,1968r:0)  0 at 1920r weight:0.000000e+00
%101 [1936r,1984r:0)  0 at 1936r weight:0.000000e+00
%102 [1952r,2000r:0)  0 at 1952r weight:0.000000e+00
%103 [1968r,2016r:0)  0 at 1968r weight:0.000000e+00
%104 [1984r,2048r:0)  0 at 1984r weight:0.000000e+00
%105 [2000r,2064r:0)  0 at 2000r weight:0.000000e+00
%106 [2016r,2080r:0)  0 at 2016r weight:0.000000e+00
%107 [640r,3968B:0)  0 at 640r weight:0.000000e+00
%108 [2032r,2112r:0)  0 at 2032r weight:0.000000e+00
%109 [2048r,2096r:0)  0 at 2048r weight:0.000000e+00
%110 [2064r,2112r:0)  0 at 2064r weight:0.000000e+00
%111 [2080r,2128r:0)  0 at 2080r weight:0.000000e+00
%112 [2096r,2160r:0)  0 at 2096r weight:0.000000e+00
%113 [2112r,2176r:0)  0 at 2112r weight:0.000000e+00
%114 [2128r,2192r:0)  0 at 2128r weight:0.000000e+00
%115 [656r,3968B:0)  0 at 656r weight:0.000000e+00
%116 [2144r,2368r:0)  0 at 2144r weight:0.000000e+00
%117 [2160r,2208r:0)  0 at 2160r weight:0.000000e+00
%118 [2176r,2224r:0)  0 at 2176r weight:0.000000e+00
%119 [2192r,2240r:0)  0 at 2192r weight:0.000000e+00
%120 [2208r,2368r:0)  0 at 2208r weight:0.000000e+00
%121 [2224r,2384r:0)  0 at 2224r weight:0.000000e+00
%122 [2240r,2400r:0)  0 at 2240r weight:0.000000e+00
%123 [672r,3968B:0)  0 at 672r weight:0.000000e+00
%124 [2256r,2640r:0)  0 at 2256r weight:0.000000e+00
%125 [2272r,2320r:0)  0 at 2272r L0000000000000002 [2272r,2304r:0)  0 at 2272r L0000000000000040 [2272r,2320r:0)  0 at 2272r weight:0.000000e+00
%126 [688r,3968B:0)  0 at 688r weight:0.000000e+00
%127 [2288r,2352r:0)  0 at 2288r L0000000000000002 [2288r,2336r:0)  0 at 2288r L0000000000000040 [2288r,2352r:0)  0 at 2288r weight:0.000000e+00
%128 [2304r,2432r:0)  0 at 2304r weight:0.000000e+00
%129 [2320r,2384r:0)  0 at 2320r weight:0.000000e+00
%130 [2336r,2448r:0)  0 at 2336r weight:0.000000e+00
%131 [2352r,2400r:0)  0 at 2352r weight:0.000000e+00
%133 [2368r,2416r:0)  0 at 2368r weight:0.000000e+00
%135 [2384r,2432r:0)  0 at 2384r weight:0.000000e+00
%136 [2400r,2448r:0)  0 at 2400r weight:0.000000e+00
%138 [2416r,2624r:0)  0 at 2416r weight:0.000000e+00
%140 [2432r,2640r:0)  0 at 2432r weight:0.000000e+00
%141 [2448r,2656r:0)  0 at 2448r weight:0.000000e+00
%142 [704r,3968B:0)  0 at 704r weight:0.000000e+00
%143 [2464r,2672r:0)  0 at 2464r weight:0.000000e+00
%144 [720r,3968B:0)  0 at 720r weight:0.000000e+00
%145 [2480r,2688r:0)  0 at 2480r weight:0.000000e+00
%146 [736r,3968B:0)  0 at 736r weight:0.000000e+00
%147 [2496r,2880r:0)  0 at 2496r weight:0.000000e+00
%148 [752r,3968B:0)  0 at 752r weight:0.000000e+00
%149 [2512r,2896r:0)  0 at 2512r weight:0.000000e+00
%150 [2528r,2576r:0)  0 at 2528r L0000000000000002 [2528r,2560r:0)  0 at 2528r L0000000000000040 [2528r,2576r:0)  0 at 2528r weight:0.000000e+00
%151 [768r,3968B:0)  0 at 768r weight:0.000000e+00
%152 [2544r,2608r:0)  0 at 2544r L0000000000000002 [2544r,2592r:0)  0 at 2544r L0000000000000040 [2544r,2608r:0)  0 at 2544r weight:0.000000e+00
%153 [2560r,2688r:0)  0 at 2560r weight:0.000000e+00
%154 [2576r,2640r:0)  0 at 2576r weight:0.000000e+00
%155 [2592r,2704r:0)  0 at 2592r weight:0.000000e+00
%156 [2608r,2656r:0)  0 at 2608r weight:0.000000e+00
%158 [2624r,2672r:0)  0 at 2624r weight:0.000000e+00
%160 [2640r,2688r:0)  0 at 2640r weight:0.000000e+00
%161 [2656r,2704r:0)  0 at 2656r weight:0.000000e+00
%163 [2672r,2880r:0)  0 at 2672r weight:0.000000e+00
%165 [2688r,2896r:0)  0 at 2688r weight:0.000000e+00
%166 [2704r,2912r:0)  0 at 2704r weight:0.000000e+00
%167 [784r,3968B:0)  0 at 784r weight:0.000000e+00
%168 [2720r,2928r:0)  0 at 2720r weight:0.000000e+00
%169 [800r,3968B:0)  0 at 800r weight:0.000000e+00
%170 [2736r,2944r:0)  0 at 2736r weight:0.000000e+00
%171 [816r,3968B:0)  0 at 816r weight:0.000000e+00
%172 [2752r,3120r:0)  0 at 2752r weight:0.000000e+00
%173 [832r,3968B:0)  0 at 832r weight:0.000000e+00
%174 [2768r,3136r:0)  0 at 2768r weight:0.000000e+00
%175 [2784r,2832r:0)  0 at 2784r L0000000000000002 [2784r,2816r:0)  0 at 2784r L0000000000000040 [2784r,2832r:0)  0 at 2784r weight:0.000000e+00
%176 [848r,3968B:0)  0 at 848r weight:0.000000e+00
%177 [2800r,2864r:0)  0 at 2800r L0000000000000002 [2800r,2848r:0)  0 at 2800r L0000000000000040 [2800r,2864r:0)  0 at 2800r weight:0.000000e+00
%178 [2816r,2944r:0)  0 at 2816r weight:0.000000e+00
%179 [2832r,2896r:0)  0 at 2832r weight:0.000000e+00
%180 [2848r,2960r:0)  0 at 2848r weight:0.000000e+00
%181 [2864r,2912r:0)  0 at 2864r weight:0.000000e+00
%183 [2880r,2928r:0)  0 at 2880r weight:0.000000e+00
%185 [2896r,2944r:0)  0 at 2896r weight:0.000000e+00
%186 [2912r,2960r:0)  0 at 2912r weight:0.000000e+00
%188 [2928r,3120r:0)  0 at 2928r weight:0.000000e+00
%190 [2944r,3136r:0)  0 at 2944r weight:0.000000e+00
%191 [2960r,3152r:0)  0 at 2960r weight:0.000000e+00
%192 [864r,3968B:0)  0 at 864r weight:0.000000e+00
%193 [2976r,3168r:0)  0 at 2976r weight:0.000000e+00
%194 [880r,3968B:0)  0 at 880r weight:0.000000e+00
%195 [2992r,3184r:0)  0 at 2992r weight:0.000000e+00
%196 [896r,3968B:0)  0 at 896r weight:0.000000e+00
%197 [3008r,3344r:0)  0 at 3008r weight:0.000000e+00
%198 [3024r,3072r:0)  0 at 3024r L0000000000000002 [3024r,3056r:0)  0 at 3024r L0000000000000040 [3024r,3072r:0)  0 at 3024r weight:0.000000e+00
%199 [912r,3968B:0)  0 at 912r weight:0.000000e+00
%200 [3040r,3104r:0)  0 at 3040r L0000000000000002 [3040r,3088r:0)  0 at 3040r L0000000000000040 [3040r,3104r:0)  0 at 3040r weight:0.000000e+00
%201 [3056r,3184r:0)  0 at 3056r weight:0.000000e+00
%202 [3072r,3136r:0)  0 at 3072r weight:0.000000e+00
%203 [3088r,3200r:0)  0 at 3088r weight:0.000000e+00
%204 [3104r,3152r:0)  0 at 3104r weight:0.000000e+00
%206 [3120r,3168r:0)  0 at 3120r weight:0.000000e+00
%208 [3136r,3184r:0)  0 at 3136r weight:0.000000e+00
%209 [3152r,3200r:0)  0 at 3152r weight:0.000000e+00
%211 [3168r,3328r:0)  0 at 3168r weight:0.000000e+00
%213 [3184r,3344r:0)  0 at 3184r weight:0.000000e+00
%214 [3200r,3360r:0)  0 at 3200r weight:0.000000e+00
%215 [928r,3968B:0)  0 at 928r weight:0.000000e+00
%216 [3216r,3584r:0)  0 at 3216r weight:0.000000e+00
%217 [3232r,3280r:0)  0 at 3232r L0000000000000002 [3232r,3264r:0)  0 at 3232r L0000000000000040 [3232r,3280r:0)  0 at 3232r weight:0.000000e+00
%218 [944r,3968B:0)  0 at 944r weight:0.000000e+00
%219 [3248r,3312r:0)  0 at 3248r L0000000000000002 [3248r,3296r:0)  0 at 3248r L0000000000000040 [3248r,3312r:0)  0 at 3248r weight:0.000000e+00
%220 [3264r,3392r:0)  0 at 3264r weight:0.000000e+00
%221 [3280r,3344r:0)  0 at 3280r weight:0.000000e+00
%222 [3296r,3408r:0)  0 at 3296r weight:0.000000e+00
%223 [3312r,3360r:0)  0 at 3312r weight:0.000000e+00
%225 [3328r,3376r:0)  0 at 3328r weight:0.000000e+00
%227 [3344r,3392r:0)  0 at 3344r weight:0.000000e+00
%228 [3360r,3408r:0)  0 at 3360r weight:0.000000e+00
%230 [3376r,3584r:0)  0 at 3376r weight:0.000000e+00
%232 [3392r,3600r:0)  0 at 3392r weight:0.000000e+00
%233 [3408r,3616r:0)  0 at 3408r weight:0.000000e+00
%234 [960r,3968B:0)  0 at 960r weight:0.000000e+00
%235 [3424r,3632r:0)  0 at 3424r weight:0.000000e+00
%236 [976r,3968B:0)  0 at 976r weight:0.000000e+00
%237 [3440r,3648r:0)  0 at 3440r weight:0.000000e+00
%238 [992r,3968B:0)  0 at 992r weight:0.000000e+00
%239 [3456r,3808r:0)  0 at 3456r weight:0.000000e+00
%240 [1008r,3968B:0)  0 at 1008r weight:0.000000e+00
%241 [3472r,3824r:0)  0 at 3472r weight:0.000000e+00
%242 [3488r,3536r:0)  0 at 3488r L0000000000000002 [3488r,3520r:0)  0 at 3488r L0000000000000040 [3488r,3536r:0)  0 at 3488r weight:0.000000e+00
%243 [1024r,3968B:0)  0 at 1024r weight:0.000000e+00
%244 [3504r,3568r:0)  0 at 3504r L0000000000000002 [3504r,3552r:0)  0 at 3504r L0000000000000040 [3504r,3568r:0)  0 at 3504r weight:0.000000e+00
%245 [3520r,3648r:0)  0 at 3520r weight:0.000000e+00
%246 [3536r,3600r:0)  0 at 3536r weight:0.000000e+00
%247 [3552r,3664r:0)  0 at 3552r weight:0.000000e+00
%248 [3568r,3616r:0)  0 at 3568r weight:0.000000e+00
%250 [3584r,3632r:0)  0 at 3584r weight:0.000000e+00
%252 [3600r,3648r:0)  0 at 3600r weight:0.000000e+00
%253 [3616r,3664r:0)  0 at 3616r weight:0.000000e+00
%255 [3632r,3808r:0)  0 at 3632r weight:0.000000e+00
%257 [3648r,3824r:0)  0 at 3648r weight:0.000000e+00
%258 [3664r,3840r:0)  0 at 3664r weight:0.000000e+00
%259 [1040r,3968B:0)  0 at 1040r weight:0.000000e+00
%260 [3680r,3856r:0)  0 at 3680r weight:0.000000e+00
%261 [1056r,3968B:0)  0 at 1056r weight:0.000000e+00
%262 [3696r,3872r:0)  0 at 3696r weight:0.000000e+00
%263 [1072r,3968B:0)  0 at 1072r weight:0.000000e+00
%264 [1088r,3968B:0)  0 at 1088r weight:0.000000e+00
%265 [3728r,3888r:0)  0 at 3728r weight:0.000000e+00
%266 [3744r,3776r:0)  0 at 3744r L0000000000000002 [3744r,3776r:0)  0 at 3744r L0000000000000040 [3744r,3744d:0)  0 at 3744r weight:0.000000e+00
%267 [1104r,3968B:0)  0 at 1104r weight:0.000000e+00
%268 [3760r,3792r:0)  0 at 3760r L0000000000000002 [3760r,3792r:0)  0 at 3760r L0000000000000040 [3760r,3760d:0)  0 at 3760r weight:0.000000e+00
%269 [3776r,3872r:0)  0 at 3776r weight:0.000000e+00
%270 [3792r,3888r:0)  0 at 3792r weight:0.000000e+00
%271 [3808r,3856r:0)  0 at 3808r weight:0.000000e+00
%272 [3824r,3872r:0)  0 at 3824r weight:0.000000e+00
%273 [3840r,3888r:0)  0 at 3840r weight:0.000000e+00
%276 [3984r,4000r:0)  0 at 3984r weight:0.000000e+00
%278 [4000r,4064r:0)  0 at 4000r weight:0.000000e+00
%280 [4048r,4064r:0)  0 at 4048r weight:0.000000e+00
%281 [4016r,4048r:0)  0 at 4016r weight:0.000000e+00
%282 [4032r,4048r:0)  0 at 4032r weight:0.000000e+00
%283 [4064r,4096r:0)  0 at 4064r weight:0.000000e+00
%284 [4080r,4096r:0)  0 at 4080r weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function test: IsSSA, TracksLiveness
Constant Pool:
  cp#0: zeroinitializer, align=32
Function Live Ins: $x3 in %24, $x4 in %25

0B	bb.0.bb:
	  successors: %bb.3(0x00000000), %bb.1(0x80000000); %bb.3(0.00%), %bb.1(100.00%)
	  liveins: $x3, $x4
16B	  %25:g8rc_and_g8rc_nox0 = COPY $x4
32B	  %24:g8rc = COPY $x3
48B	  %27:crbitrc = IMPLICIT_DEF
64B	  BC %27:crbitrc, %bb.3
80B	  B %bb.1

96B	bb.1.bb9.preheader:
	; predecessors: %bb.0
	  successors: %bb.2(0x80000000); %bb.2(100.00%)

112B	  %32:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
128B	  %33:g8rc_and_g8rc_nox0 = ADDItocL %32:g8rc_and_g8rc_nox0, %const.0, implicit $x2
144B	  %34:vsrprc = LXVP 0, %33:g8rc_and_g8rc_nox0 :: (load 32 from constant-pool)
160B	  %35:vsrc = COPY %34.sub_vsx1:vsrprc
176B	  %37:vsrprc = IMPLICIT_DEF
192B	  %36:vsrprc = INSERT_SUBREG %37:vsrprc(tied-def 0), %35:vsrc, %subreg.sub_vsx1
208B	  %38:vsrc = COPY %34.sub_vsx0:vsrprc
224B	  %39:vsrprc = INSERT_SUBREG %36:vsrprc(tied-def 0), %38:vsrc, %subreg.sub_vsx0
240B	  %40:vsrc = COPY %39.sub_vsx0:vsrprc
256B	  %41:vsrc = COPY %40:vsrc
272B	  %28:g8rc = LI8 0
288B	  %1:vsrc = LXVDSX $zero8, %28:g8rc :: (load 8 from `double* null`)
304B	  %42:vsrprc = LXVP 0, $zero8
320B	  %43:vsrc = COPY %42.sub_vsx0:vsrprc
336B	  %44:vsrc = COPY %42.sub_vsx1:vsrprc
352B	  %45:vsrc = COPY %44:vsrc
368B	  %46:vsrc = COPY %43:vsrc
384B	  %47:g8rc = LI8 -8
400B	  %5:vsrc = LXVDSX %25:g8rc_and_g8rc_nox0, %47:g8rc :: (load 8 from %ir.4)
416B	  %48:g8rc = IMPLICIT_DEF
432B	  %6:vsrc = LXVDSX $zero8, %48:g8rc :: (load 8 from `double* undef`)
448B	  %8:g8rc = COPY %25:g8rc_and_g8rc_nox0
464B	  %49:g8rc = LI8 1
480B	  MTCTR8loop %49:g8rc, implicit-def dead $ctr8
496B	  %50:vsrc = XXLXORz
512B	  %51:vsrc = COPY %50:vsrc
528B	  %30:vsrc = IMPLICIT_DEF
544B	  %29:g8rc = IMPLICIT_DEF
560B	  %31:vsrc = COPY %51:vsrc
576B	  %61:g8rc = LI8 512
592B	  %63:g8rc = LI8 528
608B	  %65:g8rc = LI8 56
624B	  %87:g8rc = LI8 616
640B	  %107:g8rc = LI8 704
656B	  %115:g8rc = LI8 744
672B	  %123:g8rc = LI8 784
688B	  %126:g8rc = LI8 312
704B	  %142:g8rc = LI8 792
720B	  %144:g8rc = LI8 800
736B	  %146:g8rc = LI8 808
752B	  %148:g8rc = LI8 816
768B	  %151:g8rc = LI8 344
784B	  %167:g8rc = LI8 824
800B	  %169:g8rc = LI8 832
816B	  %171:g8rc = LI8 840
832B	  %173:g8rc = LI8 848
848B	  %176:g8rc = LI8 376
864B	  %192:g8rc = LI8 856
880B	  %194:g8rc = LI8 864
896B	  %196:g8rc = LI8 880
912B	  %199:g8rc = LI8 408
928B	  %215:g8rc = LI8 904
944B	  %218:g8rc = LI8 440
960B	  %234:g8rc = LI8 920
976B	  %236:g8rc = LI8 928
992B	  %238:g8rc = LI8 936
1008B	  %240:g8rc = LI8 944
1024B	  %243:g8rc = LI8 472
1040B	  %259:g8rc = LI8 952
1056B	  %261:g8rc = LI8 960
1072B	  %263:g8rc = LI8 968
1088B	  %264:g8rc = LI8 976
1104B	  %267:g8rc = LI8 504

1120B	bb.2.bb9:
	; predecessors: %bb.1, %bb.2
	  successors: %bb.2(0x80000000), %bb.3(0x00000000); %bb.2(100.00%), %bb.3(0.00%)

1136B	  %9:g8rc_and_g8rc_nox0 = PHI %28:g8rc, %bb.1, %22:g8rc, %bb.2
1152B	  %10:g8rc_and_g8rc_nox0 = PHI %29:g8rc, %bb.1, %21:g8rc, %bb.2
1168B	  %11:vsrc = PHI %30:vsrc, %bb.1, %17:vsrc, %bb.2
1184B	  %12:vsrc = PHI %30:vsrc, %bb.1, %20:vsrc, %bb.2
1200B	  %13:vsrc = PHI %31:vsrc, %bb.1, %19:vsrc, %bb.2
1216B	  %14:vsrc = PHI %31:vsrc, %bb.1, %18:vsrc, %bb.2
1232B	  %15:g8rc_and_g8rc_nox0 = PHI %8:g8rc, %bb.1, %16:g8rc, %bb.2
1248B	  %16:g8rc = ADDI8 %15:g8rc_and_g8rc_nox0, 512
1264B	  %54:vsrc = contract nofpexcept XVMADDADP %14:vsrc(tied-def 0), %11:vsrc, %50:vsrc, implicit $rm
1280B	  %55:vsrc = contract nofpexcept XVMADDADP %13:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1296B	  %56:vsrc = contract nofpexcept XVMADDADP %12:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1312B	  %57:vsrc = contract nofpexcept XVMADDADP %54:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1328B	  %58:vsrc = contract nofpexcept XVMADDADP %55:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1344B	  %59:vsrc = contract nofpexcept XVMADDADP %56:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1360B	  %60:g8rc_and_g8rc_nox0 = ADD8 %24:g8rc, %9:g8rc_and_g8rc_nox0
1376B	  %62:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %61:g8rc :: (load 8 from %ir.i33.inc.cast)
1392B	  %64:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %63:g8rc :: (load 8 from %ir.scevgep123.cast)
1408B	  %66:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %65:g8rc
1424B	  %67:vsrc = COPY %66.sub_vsx1:vsrprc
1440B	  %68:vsrc = contract nofpexcept XVMADDADP %57:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1456B	  %70:vsrc = contract nofpexcept XVMADDADP %58:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1472B	  %71:vsrc = contract nofpexcept XVMADDADP %59:vsrc(tied-def 0), %67:vsrc, %62:vsrc, implicit $rm
1488B	  %72:vsrc = contract nofpexcept XVMADDADP %68:vsrc(tied-def 0), %41:vsrc, %50:vsrc, implicit $rm
1504B	  %73:vsrc = contract nofpexcept XVMADDADP %70:vsrc(tied-def 0), %41:vsrc, %62:vsrc, implicit $rm
1520B	  %74:vsrc = contract nofpexcept XVMADDADP %71:vsrc(tied-def 0), %64:vsrc, %50:vsrc, implicit $rm
1536B	  %75:vsrc = contract nofpexcept XVMADDADP %72:vsrc(tied-def 0), %45:vsrc, %50:vsrc, implicit $rm
1552B	  %76:vsrc = contract nofpexcept XVMADDADP %73:vsrc(tied-def 0), %45:vsrc, %64:vsrc, implicit $rm
1568B	  %77:vsrc = contract nofpexcept XVMADDADP %74:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1584B	  %78:vsrc = contract nofpexcept XVMADDADP %75:vsrc(tied-def 0), %46:vsrc, %50:vsrc, implicit $rm
1600B	  %79:vsrc = contract nofpexcept XVMADDADP %76:vsrc(tied-def 0), %46:vsrc, %50:vsrc, implicit $rm
1616B	  %80:vsrc = contract nofpexcept XVMADDADP %77:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1632B	  %81:vsrc = contract nofpexcept XVMADDADP %78:vsrc(tied-def 0), %1:vsrc, %50:vsrc, implicit $rm
1648B	  %82:vsrc = contract nofpexcept XVMADDADP %79:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1664B	  %83:vsrc = contract nofpexcept XVMADDADP %80:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1680B	  %84:vsrc = contract nofpexcept XVMADDADP %81:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1696B	  %85:vsrc = contract nofpexcept XVMADDADP %82:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1712B	  %86:vsrc = contract nofpexcept XVMADDADP %83:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1728B	  %88:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %87:g8rc :: (load 8 from %ir.scevgep111.cast)
1744B	  %89:vsrc = contract nofpexcept XVMADDADP %84:vsrc(tied-def 0), %5:vsrc, %50:vsrc, implicit $rm
1760B	  %90:vsrc = contract nofpexcept XVMADDADP %85:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1776B	  %91:vsrc = contract nofpexcept XVMADDADP %86:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1792B	  %92:vsrc = contract nofpexcept XVMADDADP %89:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1808B	  %93:vsrc = contract nofpexcept XVMADDADP %90:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1824B	  %94:vsrc = contract nofpexcept XVMADDADP %91:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1840B	  %95:vsrc = contract nofpexcept XVMADDADP %92:vsrc(tied-def 0), %88:vsrc, %50:vsrc, implicit $rm
1856B	  %96:vsrc = contract nofpexcept XVMADDADP %93:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1872B	  %97:vsrc = contract nofpexcept XVMADDADP %94:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1888B	  %98:vsrc = contract nofpexcept XVMADDADP %95:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1904B	  %99:vsrc = contract nofpexcept XVMADDADP %96:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1920B	  %100:vsrc = contract nofpexcept XVMADDADP %97:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1936B	  %101:vsrc = contract nofpexcept XVMADDADP %98:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1952B	  %102:vsrc = contract nofpexcept XVMADDADP %99:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1968B	  %103:vsrc = contract nofpexcept XVMADDADP %100:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1984B	  %104:vsrc = contract nofpexcept XVMADDADP %101:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2000B	  %105:vsrc = contract nofpexcept XVMADDADP %102:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2016B	  %106:vsrc = contract nofpexcept XVMADDADP %103:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2032B	  %108:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %107:g8rc :: (load 8 from %ir.scevgep126.cast)
2048B	  %109:vsrc = contract nofpexcept XVMADDADP %104:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2064B	  %110:vsrc = contract nofpexcept XVMADDADP %105:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2080B	  %111:vsrc = contract nofpexcept XVMADDADP %106:vsrc(tied-def 0), %108:vsrc, %50:vsrc, implicit $rm
2096B	  %112:vsrc = contract nofpexcept XVMADDADP %109:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2112B	  %113:vsrc = contract nofpexcept XVMADDADP %110:vsrc(tied-def 0), %108:vsrc, %50:vsrc, implicit $rm
2128B	  %114:vsrc = contract nofpexcept XVMADDADP %111:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2144B	  %116:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %115:g8rc :: (load 8 from %ir.scevgep108.cast)
2160B	  %117:vsrc = contract nofpexcept XVMADDADP %112:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2176B	  %118:vsrc = contract nofpexcept XVMADDADP %113:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2192B	  %119:vsrc = contract nofpexcept XVMADDADP %114:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2208B	  %120:vsrc = contract nofpexcept XVMADDADP %117:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2224B	  %121:vsrc = contract nofpexcept XVMADDADP %118:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2240B	  %122:vsrc = contract nofpexcept XVMADDADP %119:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2256B	  %124:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %123:g8rc :: (load 8 from %ir.scevgep129.cast)
2272B	  %125:vsrprc = LXVP 288, %10:g8rc_and_g8rc_nox0
2288B	  %127:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %126:g8rc
2304B	  %128:vsrc = COPY %125.sub_vsx0:vsrprc
2320B	  %129:vsrc = COPY %125.sub_vsx1:vsrprc
2336B	  %130:vsrc = COPY %127.sub_vsx0:vsrprc
2352B	  %131:vsrc = COPY %127.sub_vsx1:vsrprc
2368B	  %133:vsrc = contract nofpexcept XVMADDADP %120:vsrc(tied-def 0), %129:vsrc, %116:vsrc, implicit $rm
2384B	  %135:vsrc = contract nofpexcept XVMADDADP %121:vsrc(tied-def 0), %129:vsrc, %50:vsrc, implicit $rm
2400B	  %136:vsrc = contract nofpexcept XVMADDADP %122:vsrc(tied-def 0), %131:vsrc, %5:vsrc, implicit $rm
2416B	  %138:vsrc = contract nofpexcept XVMADDADP %133:vsrc(tied-def 0), %128:vsrc, %50:vsrc, implicit $rm
2432B	  %140:vsrc = contract nofpexcept XVMADDADP %135:vsrc(tied-def 0), %128:vsrc, %5:vsrc, implicit $rm
2448B	  %141:vsrc = contract nofpexcept XVMADDADP %136:vsrc(tied-def 0), %130:vsrc, %124:vsrc, implicit $rm
2464B	  %143:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %142:g8rc :: (load 8 from %ir.scevgep132.cast)
2480B	  %145:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %144:g8rc :: (load 8 from %ir.scevgep135.cast)
2496B	  %147:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %146:g8rc :: (load 8 from %ir.scevgep105.cast)
2512B	  %149:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %148:g8rc :: (load 8 from %ir.scevgep138.cast)
2528B	  %150:vsrprc = LXVP 320, %10:g8rc_and_g8rc_nox0
2544B	  %152:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %151:g8rc
2560B	  %153:vsrc = COPY %150.sub_vsx0:vsrprc
2576B	  %154:vsrc = COPY %150.sub_vsx1:vsrprc
2592B	  %155:vsrc = COPY %152.sub_vsx0:vsrprc
2608B	  %156:vsrc = COPY %152.sub_vsx1:vsrprc
2624B	  %158:vsrc = contract nofpexcept XVMADDADP %138:vsrc(tied-def 0), %154:vsrc, %50:vsrc, implicit $rm
2640B	  %160:vsrc = contract nofpexcept XVMADDADP %140:vsrc(tied-def 0), %154:vsrc, %124:vsrc, implicit $rm
2656B	  %161:vsrc = contract nofpexcept XVMADDADP %141:vsrc(tied-def 0), %156:vsrc, %145:vsrc, implicit $rm
2672B	  %163:vsrc = contract nofpexcept XVMADDADP %158:vsrc(tied-def 0), %153:vsrc, %143:vsrc, implicit $rm
2688B	  %165:vsrc = contract nofpexcept XVMADDADP %160:vsrc(tied-def 0), %153:vsrc, %145:vsrc, implicit $rm
2704B	  %166:vsrc = contract nofpexcept XVMADDADP %161:vsrc(tied-def 0), %155:vsrc, %149:vsrc, implicit $rm
2720B	  %168:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %167:g8rc :: (load 8 from %ir.scevgep141.cast)
2736B	  %170:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %169:g8rc :: (load 8 from %ir.scevgep144.cast)
2752B	  %172:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %171:g8rc :: (load 8 from %ir.scevgep102.cast)
2768B	  %174:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %173:g8rc :: (load 8 from %ir.scevgep147.cast)
2784B	  %175:vsrprc = LXVP 352, %10:g8rc_and_g8rc_nox0
2800B	  %177:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %176:g8rc
2816B	  %178:vsrc = COPY %175.sub_vsx0:vsrprc
2832B	  %179:vsrc = COPY %175.sub_vsx1:vsrprc
2848B	  %180:vsrc = COPY %177.sub_vsx0:vsrprc
2864B	  %181:vsrc = COPY %177.sub_vsx1:vsrprc
2880B	  %183:vsrc = contract nofpexcept XVMADDADP %163:vsrc(tied-def 0), %179:vsrc, %147:vsrc, implicit $rm
2896B	  %185:vsrc = contract nofpexcept XVMADDADP %165:vsrc(tied-def 0), %179:vsrc, %149:vsrc, implicit $rm
2912B	  %186:vsrc = contract nofpexcept XVMADDADP %166:vsrc(tied-def 0), %181:vsrc, %170:vsrc, implicit $rm
2928B	  %188:vsrc = contract nofpexcept XVMADDADP %183:vsrc(tied-def 0), %178:vsrc, %168:vsrc, implicit $rm
2944B	  %190:vsrc = contract nofpexcept XVMADDADP %185:vsrc(tied-def 0), %178:vsrc, %170:vsrc, implicit $rm
2960B	  %191:vsrc = contract nofpexcept XVMADDADP %186:vsrc(tied-def 0), %180:vsrc, %174:vsrc, implicit $rm
2976B	  %193:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %192:g8rc :: (load 8 from %ir.scevgep150.cast)
2992B	  %195:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %194:g8rc :: (load 8 from %ir.scevgep153.cast)
3008B	  %197:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %196:g8rc :: (load 8 from %ir.scevgep156.cast)
3024B	  %198:vsrprc = LXVP 384, %10:g8rc_and_g8rc_nox0
3040B	  %200:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %199:g8rc
3056B	  %201:vsrc = COPY %198.sub_vsx0:vsrprc
3072B	  %202:vsrc = COPY %198.sub_vsx1:vsrprc
3088B	  %203:vsrc = COPY %200.sub_vsx0:vsrprc
3104B	  %204:vsrc = COPY %200.sub_vsx1:vsrprc
3120B	  %206:vsrc = contract nofpexcept XVMADDADP %188:vsrc(tied-def 0), %202:vsrc, %172:vsrc, implicit $rm
3136B	  %208:vsrc = contract nofpexcept XVMADDADP %190:vsrc(tied-def 0), %202:vsrc, %174:vsrc, implicit $rm
3152B	  %209:vsrc = contract nofpexcept XVMADDADP %191:vsrc(tied-def 0), %204:vsrc, %195:vsrc, implicit $rm
3168B	  %211:vsrc = contract nofpexcept XVMADDADP %206:vsrc(tied-def 0), %201:vsrc, %193:vsrc, implicit $rm
3184B	  %213:vsrc = contract nofpexcept XVMADDADP %208:vsrc(tied-def 0), %201:vsrc, %195:vsrc, implicit $rm
3200B	  %214:vsrc = contract nofpexcept XVMADDADP %209:vsrc(tied-def 0), %203:vsrc, %197:vsrc, implicit $rm
3216B	  %216:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %215:g8rc :: (load 8 from %ir.scevgep99.cast)
3232B	  %217:vsrprc = LXVP 416, %10:g8rc_and_g8rc_nox0
3248B	  %219:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %218:g8rc
3264B	  %220:vsrc = COPY %217.sub_vsx0:vsrprc
3280B	  %221:vsrc = COPY %217.sub_vsx1:vsrprc
3296B	  %222:vsrc = COPY %219.sub_vsx0:vsrprc
3312B	  %223:vsrc = COPY %219.sub_vsx1:vsrprc
3328B	  %225:vsrc = contract nofpexcept XVMADDADP %211:vsrc(tied-def 0), %221:vsrc, %50:vsrc, implicit $rm
3344B	  %227:vsrc = contract nofpexcept XVMADDADP %213:vsrc(tied-def 0), %221:vsrc, %197:vsrc, implicit $rm
3360B	  %228:vsrc = contract nofpexcept XVMADDADP %214:vsrc(tied-def 0), %223:vsrc, %6:vsrc, implicit $rm
3376B	  %230:vsrc = contract nofpexcept XVMADDADP %225:vsrc(tied-def 0), %220:vsrc, %50:vsrc, implicit $rm
3392B	  %232:vsrc = contract nofpexcept XVMADDADP %227:vsrc(tied-def 0), %220:vsrc, %6:vsrc, implicit $rm
3408B	  %233:vsrc = contract nofpexcept XVMADDADP %228:vsrc(tied-def 0), %222:vsrc, %6:vsrc, implicit $rm
3424B	  %235:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %234:g8rc :: (load 8 from %ir.scevgep159.cast)
3440B	  %237:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %236:g8rc :: (load 8 from %ir.scevgep162.cast)
3456B	  %239:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %238:g8rc :: (load 8 from %ir.scevgep96.cast)
3472B	  %241:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %240:g8rc :: (load 8 from %ir.scevgep165.cast)
3488B	  %242:vsrprc = LXVP 448, %10:g8rc_and_g8rc_nox0
3504B	  %244:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %243:g8rc
3520B	  %245:vsrc = COPY %242.sub_vsx0:vsrprc
3536B	  %246:vsrc = COPY %242.sub_vsx1:vsrprc
3552B	  %247:vsrc = COPY %244.sub_vsx0:vsrprc
3568B	  %248:vsrc = COPY %244.sub_vsx1:vsrprc
3584B	  %250:vsrc = contract nofpexcept XVMADDADP %230:vsrc(tied-def 0), %246:vsrc, %216:vsrc, implicit $rm
3600B	  %252:vsrc = contract nofpexcept XVMADDADP %232:vsrc(tied-def 0), %246:vsrc, %6:vsrc, implicit $rm
3616B	  %253:vsrc = contract nofpexcept XVMADDADP %233:vsrc(tied-def 0), %248:vsrc, %237:vsrc, implicit $rm
3632B	  %255:vsrc = contract nofpexcept XVMADDADP %250:vsrc(tied-def 0), %245:vsrc, %235:vsrc, implicit $rm
3648B	  %257:vsrc = contract nofpexcept XVMADDADP %252:vsrc(tied-def 0), %245:vsrc, %237:vsrc, implicit $rm
3664B	  %258:vsrc = contract nofpexcept XVMADDADP %253:vsrc(tied-def 0), %247:vsrc, %241:vsrc, implicit $rm
3680B	  %260:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %259:g8rc :: (load 8 from %ir.scevgep117.cast)
3696B	  %262:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %261:g8rc :: (load 8 from %ir.scevgep114.cast)
3712B	  %17:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %263:g8rc :: (load 8 from %ir.scevgep93.cast)
3728B	  %265:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %264:g8rc :: (load 8 from %ir.uglygep8990.cast)
3744B	  %266:vsrprc = LXVP 480, %10:g8rc_and_g8rc_nox0
3760B	  %268:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %267:g8rc
3776B	  %269:vsrc = COPY %266.sub_vsx0:vsrprc
3792B	  %270:vsrc = COPY %268.sub_vsx0:vsrprc
3808B	  %271:vsrc = contract nofpexcept XVMADDADP %255:vsrc(tied-def 0), %239:vsrc, %50:vsrc, implicit $rm
3824B	  %272:vsrc = contract nofpexcept XVMADDADP %257:vsrc(tied-def 0), %241:vsrc, %50:vsrc, implicit $rm
3840B	  %273:vsrc = contract nofpexcept XVMADDADP %258:vsrc(tied-def 0), %262:vsrc, %50:vsrc, implicit $rm
3856B	  %18:vsrc = contract nofpexcept XVMADDADP %271:vsrc(tied-def 0), %269:vsrc, %260:vsrc, implicit $rm
3872B	  %19:vsrc = contract nofpexcept XVMADDADP %272:vsrc(tied-def 0), %269:vsrc, %262:vsrc, implicit $rm
3888B	  %20:vsrc = contract nofpexcept XVMADDADP %273:vsrc(tied-def 0), %270:vsrc, %265:vsrc, implicit $rm
3904B	  %21:g8rc = nsw ADDI8 %10:g8rc_and_g8rc_nox0, 512
3920B	  %22:g8rc = ADDI8 %9:g8rc_and_g8rc_nox0, 512
3936B	  BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8
3952B	  B %bb.3

3968B	bb.3.bb421:
	; predecessors: %bb.0, %bb.2

3984B	  %276:vsrc = XXLXORz
4000B	  %278:vrrc = XXSPLTI32DX %276:vsrc(tied-def 0), 0, 2146959360
4016B	  %281:vsrprc = IMPLICIT_DEF
4032B	  %282:vrrc = IMPLICIT_DEF
4048B	  %280:vsrprc = INSERT_SUBREG %281:vsrprc(tied-def 0), %282:vrrc, %subreg.sub_vsx1
4064B	  %283:vsrprc = INSERT_SUBREG %280:vsrprc(tied-def 0), %278:vrrc, %subreg.sub_vsx0
4080B	  %284:g8rc_and_g8rc_nox0 = IMPLICIT_DEF
4096B	  STXVP %283:vsrprc, 0, %284:g8rc_and_g8rc_nox0

# End machine code for function test.

Computing live-in reg-units in ABI blocks.
0B	%bb.0 R3#0 R4#0
Created 2 new intervals.
********** INTERVALS **********
R3 [0B,32r:0)  0 at 0B-phi
R4 [0B,16r:0)  0 at 0B-phi
%1 [272r,5664B:0)  0 at 272r weight:0.000000e+00
%5 [384r,5664B:0)  0 at 384r weight:0.000000e+00
%6 [400r,5664B:0)  0 at 400r weight:0.000000e+00
%8 [416r,1152r:0)  0 at 416r weight:0.000000e+00
%9 [1280r,5504r:0)  0 at 1280r weight:0.000000e+00
%10 [1264r,5488r:0)  0 at 1264r weight:0.000000e+00
%11 [1248r,1328r:0)  0 at 1248r weight:0.000000e+00
%12 [1232r,1376r:0)  0 at 1232r weight:0.000000e+00
%13 [1216r,1344r:0)  0 at 1216r weight:0.000000e+00
%14 [1200r,1312r:0)  0 at 1200r weight:0.000000e+00
%15 [1184r,5216r:0)  0 at 1184r weight:0.000000e+00
%16 [1296r,5616r:0)  0 at 1296r weight:0.000000e+00
%17 [5200r,5552r:0)  0 at 5200r weight:0.000000e+00
%18 [5392r,5408r:0)[5408r,5600r:1)  0 at 5392r 1 at 5408r weight:0.000000e+00
%19 [5424r,5440r:0)[5440r,5584r:1)  0 at 5424r 1 at 5440r weight:0.000000e+00
%20 [5456r,5472r:0)[5472r,5568r:1)  0 at 5456r 1 at 5472r weight:0.000000e+00
%21 [5488r,5536r:0)  0 at 5488r weight:0.000000e+00
%22 [5504r,5520r:0)  0 at 5504r weight:0.000000e+00
%24 [32r,5664B:0)  0 at 32r weight:0.000000e+00
%25 [16r,416r:0)  0 at 16r weight:0.000000e+00
%27 EMPTY weight:0.000000e+00
%28 [256r,1056r:0)  0 at 256r weight:0.000000e+00
%31 [496r,1136r:0)  0 at 496r weight:0.000000e+00
%32 [96r,112r:0)  0 at 96r weight:0.000000e+00
%33 [112r,128r:0)  0 at 112r weight:0.000000e+00
%34 [128r,176r:0)  0 at 128r L0000000000000040 [128r,144r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r weight:0.000000e+00
%35 [144r,160r:0)  0 at 144r weight:0.000000e+00
%36 [160r,192r:0)  0 at 160r L0000000000000040 [160r,192r:0)  0 at 160r weight:0.000000e+00
%38 [176r,208r:0)  0 at 176r weight:0.000000e+00
%39 [192r,208r:0)[208r,224r:1)  0 at 192r 1 at 208r L0000000000000002 [192r,192d:0)[208r,224r:1)  0 at 192r 1 at 208r L0000000000000040 [192r,192d:0)  0 at 192r weight:0.000000e+00
%40 [224r,240r:0)  0 at 224r weight:0.000000e+00
%41 [240r,5664B:0)  0 at 240r weight:0.000000e+00
%42 [288r,320r:0)  0 at 288r L0000000000000002 [288r,304r:0)  0 at 288r L0000000000000040 [288r,320r:0)  0 at 288r weight:0.000000e+00
%43 [304r,352r:0)  0 at 304r weight:0.000000e+00
%44 [320r,336r:0)  0 at 320r weight:0.000000e+00
%45 [336r,5664B:0)  0 at 336r weight:0.000000e+00
%46 [352r,5664B:0)  0 at 352r weight:0.000000e+00
%47 [368r,384r:0)  0 at 368r weight:0.000000e+00
%48 EMPTY weight:0.000000e+00
%49 [432r,448r:0)  0 at 432r weight:0.000000e+00
%50 [464r,5664B:0)  0 at 464r weight:0.000000e+00
%51 [480r,496r:0)  0 at 480r weight:0.000000e+00
%54 [1312r,1328r:0)[1328r,1408r:1)  0 at 1312r 1 at 1328r weight:0.000000e+00
%55 [1344r,1360r:0)[1360r,1440r:1)  0 at 1344r 1 at 1360r weight:0.000000e+00
%56 [1376r,1392r:0)[1392r,1472r:1)  0 at 1376r 1 at 1392r weight:0.000000e+00
%57 [1408r,1424r:0)[1424r,1584r:1)  0 at 1408r 1 at 1424r weight:0.000000e+00
%58 [1440r,1456r:0)[1456r,1616r:1)  0 at 1440r 1 at 1456r weight:0.000000e+00
%59 [1472r,1488r:0)[1488r,1648r:1)  0 at 1472r 1 at 1488r weight:0.000000e+00
%60 [1504r,5248r:0)  0 at 1504r weight:0.000000e+00
%61 [512r,5664B:0)  0 at 512r weight:0.000000e+00
%62 [1520r,1728r:0)  0 at 1520r weight:0.000000e+00
%63 [528r,5664B:0)  0 at 528r weight:0.000000e+00
%64 [1536r,1824r:0)  0 at 1536r weight:0.000000e+00
%65 [544r,5664B:0)  0 at 544r weight:0.000000e+00
%66 [1552r,1568r:0)  0 at 1552r L0000000000000040 [1552r,1568r:0)  0 at 1552r L0000000000000002 [1552r,1552d:0)  0 at 1552r weight:0.000000e+00
%67 [1568r,1664r:0)  0 at 1568r weight:0.000000e+00
%68 [1584r,1600r:0)[1600r,1680r:1)  0 at 1584r 1 at 1600r weight:0.000000e+00
%70 [1616r,1632r:0)[1632r,1712r:1)  0 at 1616r 1 at 1632r weight:0.000000e+00
%71 [1648r,1664r:0)[1664r,1744r:1)  0 at 1648r 1 at 1664r weight:0.000000e+00
%72 [1680r,1696r:0)[1696r,1776r:1)  0 at 1680r 1 at 1696r weight:0.000000e+00
%73 [1712r,1728r:0)[1728r,1808r:1)  0 at 1712r 1 at 1728r weight:0.000000e+00
%74 [1744r,1760r:0)[1760r,1840r:1)  0 at 1744r 1 at 1760r weight:0.000000e+00
%75 [1776r,1792r:0)[1792r,1872r:1)  0 at 1776r 1 at 1792r weight:0.000000e+00
%76 [1808r,1824r:0)[1824r,1904r:1)  0 at 1808r 1 at 1824r weight:0.000000e+00
%77 [1840r,1856r:0)[1856r,1936r:1)  0 at 1840r 1 at 1856r weight:0.000000e+00
%78 [1872r,1888r:0)[1888r,1968r:1)  0 at 1872r 1 at 1888r weight:0.000000e+00
%79 [1904r,1920r:0)[1920r,2000r:1)  0 at 1904r 1 at 1920r weight:0.000000e+00
%80 [1936r,1952r:0)[1952r,2032r:1)  0 at 1936r 1 at 1952r weight:0.000000e+00
%81 [1968r,1984r:0)[1984r,2064r:1)  0 at 1968r 1 at 1984r weight:0.000000e+00
%82 [2000r,2016r:0)[2016r,2096r:1)  0 at 2000r 1 at 2016r weight:0.000000e+00
%83 [2032r,2048r:0)[2048r,2128r:1)  0 at 2032r 1 at 2048r weight:0.000000e+00
%84 [2064r,2080r:0)[2080r,2176r:1)  0 at 2064r 1 at 2080r weight:0.000000e+00
%85 [2096r,2112r:0)[2112r,2208r:1)  0 at 2096r 1 at 2112r weight:0.000000e+00
%86 [2128r,2144r:0)[2144r,2240r:1)  0 at 2128r 1 at 2144r weight:0.000000e+00
%87 [560r,5664B:0)  0 at 560r weight:0.000000e+00
%88 [2160r,2384r:0)  0 at 2160r weight:0.000000e+00
%89 [2176r,2192r:0)[2192r,2272r:1)  0 at 2176r 1 at 2192r weight:0.000000e+00
%90 [2208r,2224r:0)[2224r,2304r:1)  0 at 2208r 1 at 2224r weight:0.000000e+00
%91 [2240r,2256r:0)[2256r,2336r:1)  0 at 2240r 1 at 2256r weight:0.000000e+00
%92 [2272r,2288r:0)[2288r,2368r:1)  0 at 2272r 1 at 2288r weight:0.000000e+00
%93 [2304r,2320r:0)[2320r,2400r:1)  0 at 2304r 1 at 2320r weight:0.000000e+00
%94 [2336r,2352r:0)[2352r,2432r:1)  0 at 2336r 1 at 2352r weight:0.000000e+00
%95 [2368r,2384r:0)[2384r,2464r:1)  0 at 2368r 1 at 2384r weight:0.000000e+00
%96 [2400r,2416r:0)[2416r,2496r:1)  0 at 2400r 1 at 2416r weight:0.000000e+00
%97 [2432r,2448r:0)[2448r,2528r:1)  0 at 2432r 1 at 2448r weight:0.000000e+00
%98 [2464r,2480r:0)[2480r,2560r:1)  0 at 2464r 1 at 2480r weight:0.000000e+00
%99 [2496r,2512r:0)[2512r,2592r:1)  0 at 2496r 1 at 2512r weight:0.000000e+00
%100 [2528r,2544r:0)[2544r,2624r:1)  0 at 2528r 1 at 2544r weight:0.000000e+00
%101 [2560r,2576r:0)[2576r,2656r:1)  0 at 2560r 1 at 2576r weight:0.000000e+00
%102 [2592r,2608r:0)[2608r,2688r:1)  0 at 2592r 1 at 2608r weight:0.000000e+00
%103 [2624r,2640r:0)[2640r,2720r:1)  0 at 2624r 1 at 2640r weight:0.000000e+00
%104 [2656r,2672r:0)[2672r,2768r:1)  0 at 2656r 1 at 2672r weight:0.000000e+00
%105 [2688r,2704r:0)[2704r,2800r:1)  0 at 2688r 1 at 2704r weight:0.000000e+00
%106 [2720r,2736r:0)[2736r,2832r:1)  0 at 2720r 1 at 2736r weight:0.000000e+00
%107 [576r,5664B:0)  0 at 576r weight:0.000000e+00
%108 [2752r,2912r:0)  0 at 2752r weight:0.000000e+00
%109 [2768r,2784r:0)[2784r,2864r:1)  0 at 2768r 1 at 2784r weight:0.000000e+00
%110 [2800r,2816r:0)[2816r,2896r:1)  0 at 2800r 1 at 2816r weight:0.000000e+00
%111 [2832r,2848r:0)[2848r,2928r:1)  0 at 2832r 1 at 2848r weight:0.000000e+00
%112 [2864r,2880r:0)[2880r,2976r:1)  0 at 2864r 1 at 2880r weight:0.000000e+00
%113 [2896r,2912r:0)[2912r,3008r:1)  0 at 2896r 1 at 2912r weight:0.000000e+00
%114 [2928r,2944r:0)[2944r,3040r:1)  0 at 2928r 1 at 2944r weight:0.000000e+00
%115 [592r,5664B:0)  0 at 592r weight:0.000000e+00
%116 [2960r,3296r:0)  0 at 2960r weight:0.000000e+00
%117 [2976r,2992r:0)[2992r,3072r:1)  0 at 2976r 1 at 2992r weight:0.000000e+00
%118 [3008r,3024r:0)[3024r,3104r:1)  0 at 3008r 1 at 3024r weight:0.000000e+00
%119 [3040r,3056r:0)[3056r,3136r:1)  0 at 3040r 1 at 3056r weight:0.000000e+00
%120 [3072r,3088r:0)[3088r,3280r:1)  0 at 3072r 1 at 3088r weight:0.000000e+00
%121 [3104r,3120r:0)[3120r,3312r:1)  0 at 3104r 1 at 3120r weight:0.000000e+00
%122 [3136r,3152r:0)[3152r,3344r:1)  0 at 3136r 1 at 3152r weight:0.000000e+00
%123 [608r,5664B:0)  0 at 608r weight:0.000000e+00
%124 [3168r,3680r:0)  0 at 3168r weight:0.000000e+00
%125 [3184r,3232r:0)  0 at 3184r L0000000000000002 [3184r,3216r:0)  0 at 3184r L0000000000000040 [3184r,3232r:0)  0 at 3184r weight:0.000000e+00
%126 [624r,5664B:0)  0 at 624r weight:0.000000e+00
%127 [3200r,3264r:0)  0 at 3200r L0000000000000002 [3200r,3248r:0)  0 at 3200r L0000000000000040 [3200r,3264r:0)  0 at 3200r weight:0.000000e+00
%128 [3216r,3424r:0)  0 at 3216r weight:0.000000e+00
%129 [3232r,3328r:0)  0 at 3232r weight:0.000000e+00
%130 [3248r,3456r:0)  0 at 3248r weight:0.000000e+00
%131 [3264r,3360r:0)  0 at 3264r weight:0.000000e+00
%133 [3280r,3296r:0)[3296r,3376r:1)  0 at 3280r 1 at 3296r weight:0.000000e+00
%135 [3312r,3328r:0)[3328r,3408r:1)  0 at 3312r 1 at 3328r weight:0.000000e+00
%136 [3344r,3360r:0)[3360r,3440r:1)  0 at 3344r 1 at 3360r weight:0.000000e+00
%138 [3376r,3392r:0)[3392r,3632r:1)  0 at 3376r 1 at 3392r weight:0.000000e+00
%140 [3408r,3424r:0)[3424r,3664r:1)  0 at 3408r 1 at 3424r weight:0.000000e+00
%141 [3440r,3456r:0)[3456r,3696r:1)  0 at 3440r 1 at 3456r weight:0.000000e+00
%142 [640r,5664B:0)  0 at 640r weight:0.000000e+00
%143 [3472r,3744r:0)  0 at 3472r weight:0.000000e+00
%144 [656r,5664B:0)  0 at 656r weight:0.000000e+00
%145 [3488r,3776r:0)  0 at 3488r weight:0.000000e+00
%146 [672r,5664B:0)  0 at 672r weight:0.000000e+00
%147 [3504r,4000r:0)  0 at 3504r weight:0.000000e+00
%148 [688r,5664B:0)  0 at 688r weight:0.000000e+00
%149 [3520r,4032r:0)  0 at 3520r weight:0.000000e+00
%150 [3536r,3584r:0)  0 at 3536r L0000000000000002 [3536r,3568r:0)  0 at 3536r L0000000000000040 [3536r,3584r:0)  0 at 3536r weight:0.000000e+00
%151 [704r,5664B:0)  0 at 704r weight:0.000000e+00
%152 [3552r,3616r:0)  0 at 3552r L0000000000000002 [3552r,3600r:0)  0 at 3552r L0000000000000040 [3552r,3616r:0)  0 at 3552r weight:0.000000e+00
%153 [3568r,3776r:0)  0 at 3568r weight:0.000000e+00
%154 [3584r,3680r:0)  0 at 3584r weight:0.000000e+00
%155 [3600r,3808r:0)  0 at 3600r weight:0.000000e+00
%156 [3616r,3712r:0)  0 at 3616r weight:0.000000e+00
%158 [3632r,3648r:0)[3648r,3728r:1)  0 at 3632r 1 at 3648r weight:0.000000e+00
%160 [3664r,3680r:0)[3680r,3760r:1)  0 at 3664r 1 at 3680r weight:0.000000e+00
%161 [3696r,3712r:0)[3712r,3792r:1)  0 at 3696r 1 at 3712r weight:0.000000e+00
%163 [3728r,3744r:0)[3744r,3984r:1)  0 at 3728r 1 at 3744r weight:0.000000e+00
%165 [3760r,3776r:0)[3776r,4016r:1)  0 at 3760r 1 at 3776r weight:0.000000e+00
%166 [3792r,3808r:0)[3808r,4048r:1)  0 at 3792r 1 at 3808r weight:0.000000e+00
%167 [720r,5664B:0)  0 at 720r weight:0.000000e+00
%168 [3824r,4096r:0)  0 at 3824r weight:0.000000e+00
%169 [736r,5664B:0)  0 at 736r weight:0.000000e+00
%170 [3840r,4128r:0)  0 at 3840r weight:0.000000e+00
%171 [752r,5664B:0)  0 at 752r weight:0.000000e+00
%172 [3856r,4336r:0)  0 at 3856r weight:0.000000e+00
%173 [768r,5664B:0)  0 at 768r weight:0.000000e+00
%174 [3872r,4368r:0)  0 at 3872r weight:0.000000e+00
%175 [3888r,3936r:0)  0 at 3888r L0000000000000002 [3888r,3920r:0)  0 at 3888r L0000000000000040 [3888r,3936r:0)  0 at 3888r weight:0.000000e+00
%176 [784r,5664B:0)  0 at 784r weight:0.000000e+00
%177 [3904r,3968r:0)  0 at 3904r L0000000000000002 [3904r,3952r:0)  0 at 3904r L0000000000000040 [3904r,3968r:0)  0 at 3904r weight:0.000000e+00
%178 [3920r,4128r:0)  0 at 3920r weight:0.000000e+00
%179 [3936r,4032r:0)  0 at 3936r weight:0.000000e+00
%180 [3952r,4160r:0)  0 at 3952r weight:0.000000e+00
%181 [3968r,4064r:0)  0 at 3968r weight:0.000000e+00
%183 [3984r,4000r:0)[4000r,4080r:1)  0 at 3984r 1 at 4000r weight:0.000000e+00
%185 [4016r,4032r:0)[4032r,4112r:1)  0 at 4016r 1 at 4032r weight:0.000000e+00
%186 [4048r,4064r:0)[4064r,4144r:1)  0 at 4048r 1 at 4064r weight:0.000000e+00
%188 [4080r,4096r:0)[4096r,4320r:1)  0 at 4080r 1 at 4096r weight:0.000000e+00
%190 [4112r,4128r:0)[4128r,4352r:1)  0 at 4112r 1 at 4128r weight:0.000000e+00
%191 [4144r,4160r:0)[4160r,4384r:1)  0 at 4144r 1 at 4160r weight:0.000000e+00
%192 [800r,5664B:0)  0 at 800r weight:0.000000e+00
%193 [4176r,4432r:0)  0 at 4176r weight:0.000000e+00
%194 [816r,5664B:0)  0 at 816r weight:0.000000e+00
%195 [4192r,4464r:0)  0 at 4192r weight:0.000000e+00
%196 [832r,5664B:0)  0 at 832r weight:0.000000e+00
%197 [4208r,4672r:0)  0 at 4208r weight:0.000000e+00
%198 [4224r,4272r:0)  0 at 4224r L0000000000000002 [4224r,4256r:0)  0 at 4224r L0000000000000040 [4224r,4272r:0)  0 at 4224r weight:0.000000e+00
%199 [848r,5664B:0)  0 at 848r weight:0.000000e+00
%200 [4240r,4304r:0)  0 at 4240r L0000000000000002 [4240r,4288r:0)  0 at 4240r L0000000000000040 [4240r,4304r:0)  0 at 4240r weight:0.000000e+00
%201 [4256r,4464r:0)  0 at 4256r weight:0.000000e+00
%202 [4272r,4368r:0)  0 at 4272r weight:0.000000e+00
%203 [4288r,4496r:0)  0 at 4288r weight:0.000000e+00
%204 [4304r,4400r:0)  0 at 4304r weight:0.000000e+00
%206 [4320r,4336r:0)[4336r,4416r:1)  0 at 4320r 1 at 4336r weight:0.000000e+00
%208 [4352r,4368r:0)[4368r,4448r:1)  0 at 4352r 1 at 4368r weight:0.000000e+00
%209 [4384r,4400r:0)[4400r,4480r:1)  0 at 4384r 1 at 4400r weight:0.000000e+00
%211 [4416r,4432r:0)[4432r,4624r:1)  0 at 4416r 1 at 4432r weight:0.000000e+00
%213 [4448r,4464r:0)[4464r,4656r:1)  0 at 4448r 1 at 4464r weight:0.000000e+00
%214 [4480r,4496r:0)[4496r,4688r:1)  0 at 4480r 1 at 4496r weight:0.000000e+00
%215 [864r,5664B:0)  0 at 864r weight:0.000000e+00
%216 [4512r,4992r:0)  0 at 4512r weight:0.000000e+00
%217 [4528r,4576r:0)  0 at 4528r L0000000000000002 [4528r,4560r:0)  0 at 4528r L0000000000000040 [4528r,4576r:0)  0 at 4528r weight:0.000000e+00
%218 [880r,5664B:0)  0 at 880r weight:0.000000e+00
%219 [4544r,4608r:0)  0 at 4544r L0000000000000002 [4544r,4592r:0)  0 at 4544r L0000000000000040 [4544r,4608r:0)  0 at 4544r weight:0.000000e+00
%220 [4560r,4768r:0)  0 at 4560r weight:0.000000e+00
%221 [4576r,4672r:0)  0 at 4576r weight:0.000000e+00
%222 [4592r,4800r:0)  0 at 4592r weight:0.000000e+00
%223 [4608r,4704r:0)  0 at 4608r weight:0.000000e+00
%225 [4624r,4640r:0)[4640r,4720r:1)  0 at 4624r 1 at 4640r weight:0.000000e+00
%227 [4656r,4672r:0)[4672r,4752r:1)  0 at 4656r 1 at 4672r weight:0.000000e+00
%228 [4688r,4704r:0)[4704r,4784r:1)  0 at 4688r 1 at 4704r weight:0.000000e+00
%230 [4720r,4736r:0)[4736r,4976r:1)  0 at 4720r 1 at 4736r weight:0.000000e+00
%232 [4752r,4768r:0)[4768r,5008r:1)  0 at 4752r 1 at 4768r weight:0.000000e+00
%233 [4784r,4800r:0)[4800r,5040r:1)  0 at 4784r 1 at 4800r weight:0.000000e+00
%234 [896r,5664B:0)  0 at 896r weight:0.000000e+00
%235 [4816r,5088r:0)  0 at 4816r weight:0.000000e+00
%236 [912r,5664B:0)  0 at 912r weight:0.000000e+00
%237 [4832r,5120r:0)  0 at 4832r weight:0.000000e+00
%238 [928r,5664B:0)  0 at 928r weight:0.000000e+00
%239 [4848r,5312r:0)  0 at 4848r weight:0.000000e+00
%240 [944r,5664B:0)  0 at 944r weight:0.000000e+00
%241 [4864r,5344r:0)  0 at 4864r weight:0.000000e+00
%242 [4880r,4928r:0)  0 at 4880r L0000000000000002 [4880r,4912r:0)  0 at 4880r L0000000000000040 [4880r,4928r:0)  0 at 4880r weight:0.000000e+00
%243 [960r,5664B:0)  0 at 960r weight:0.000000e+00
%244 [4896r,4960r:0)  0 at 4896r L0000000000000002 [4896r,4944r:0)  0 at 4896r L0000000000000040 [4896r,4960r:0)  0 at 4896r weight:0.000000e+00
%245 [4912r,5120r:0)  0 at 4912r weight:0.000000e+00
%246 [4928r,5024r:0)  0 at 4928r weight:0.000000e+00
%247 [4944r,5152r:0)  0 at 4944r weight:0.000000e+00
%248 [4960r,5056r:0)  0 at 4960r weight:0.000000e+00
%250 [4976r,4992r:0)[4992r,5072r:1)  0 at 4976r 1 at 4992r weight:0.000000e+00
%252 [5008r,5024r:0)[5024r,5104r:1)  0 at 5008r 1 at 5024r weight:0.000000e+00
%253 [5040r,5056r:0)[5056r,5136r:1)  0 at 5040r 1 at 5056r weight:0.000000e+00
%255 [5072r,5088r:0)[5088r,5296r:1)  0 at 5072r 1 at 5088r weight:0.000000e+00
%257 [5104r,5120r:0)[5120r,5328r:1)  0 at 5104r 1 at 5120r weight:0.000000e+00
%258 [5136r,5152r:0)[5152r,5360r:1)  0 at 5136r 1 at 5152r weight:0.000000e+00
%259 [976r,5664B:0)  0 at 976r weight:0.000000e+00
%260 [5168r,5408r:0)  0 at 5168r weight:0.000000e+00
%261 [992r,5664B:0)  0 at 992r weight:0.000000e+00
%262 [5184r,5440r:0)  0 at 5184r weight:0.000000e+00
%263 [1008r,5664B:0)  0 at 1008r weight:0.000000e+00
%264 [1024r,5664B:0)  0 at 1024r weight:0.000000e+00
%265 [5216r,5472r:0)  0 at 5216r weight:0.000000e+00
%266 [5232r,5264r:0)  0 at 5232r L0000000000000002 [5232r,5264r:0)  0 at 5232r L0000000000000040 [5232r,5232d:0)  0 at 5232r weight:0.000000e+00
%267 [1040r,5664B:0)  0 at 1040r weight:0.000000e+00
%268 [5248r,5280r:0)  0 at 5248r L0000000000000002 [5248r,5280r:0)  0 at 5248r L0000000000000040 [5248r,5248d:0)  0 at 5248r weight:0.000000e+00
%269 [5264r,5440r:0)  0 at 5264r weight:0.000000e+00
%270 [5280r,5472r:0)  0 at 5280r weight:0.000000e+00
%271 [5296r,5312r:0)[5312r,5392r:1)  0 at 5296r 1 at 5312r weight:0.000000e+00
%272 [5328r,5344r:0)[5344r,5424r:1)  0 at 5328r 1 at 5344r weight:0.000000e+00
%273 [5360r,5376r:0)[5376r,5456r:1)  0 at 5360r 1 at 5376r weight:0.000000e+00
%276 [5680r,5696r:0)  0 at 5680r weight:0.000000e+00
%278 [5696r,5712r:0)[5712r,5728r:1)  0 at 5696r 1 at 5712r weight:0.000000e+00
%283 [5728r,5744r:0)  0 at 5728r L0000000000000002 [5728r,5744r:0)  0 at 5728r weight:0.000000e+00
%284 EMPTY weight:0.000000e+00
%285 [1056r,1168B:0)[1168B,1280r:2)[5520r,5664B:1)  0 at 1056r 1 at 5520r 2 at 1168B-phi weight:0.000000e+00
%286 [1072r,1168B:0)[1168B,1264r:2)[5536r,5664B:1)  0 at 1072r 1 at 5536r 2 at 1168B-phi weight:0.000000e+00
%287 [1088r,1168B:0)[1168B,1248r:2)[5552r,5664B:1)  0 at 1088r 1 at 5552r 2 at 1168B-phi weight:0.000000e+00
%288 [1104r,1168B:0)[1168B,1232r:2)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi weight:0.000000e+00
%289 [1120r,1168B:0)[1168B,1216r:2)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi weight:0.000000e+00
%290 [1136r,1168B:0)[1168B,1200r:2)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi weight:0.000000e+00
%291 [1152r,1168B:0)[1168B,1184r:2)[5616r,5664B:1)  0 at 1152r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function test: NoPHIs, TracksLiveness, TiedOpsRewritten
Constant Pool:
  cp#0: zeroinitializer, align=32
Function Live Ins: $x3 in %24, $x4 in %25

0B	bb.0.bb:
	  successors: %bb.3(0x00000000), %bb.1(0x80000000); %bb.3(0.00%), %bb.1(100.00%)
	  liveins: $x3, $x4
16B	  %25:g8rc_and_g8rc_nox0 = COPY $x4
32B	  %24:g8rc = COPY $x3
48B	  BC undef %27:crbitrc, %bb.3
64B	  B %bb.1

80B	bb.1.bb9.preheader:
	; predecessors: %bb.0
	  successors: %bb.2(0x80000000); %bb.2(100.00%)

96B	  %32:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
112B	  %33:g8rc_and_g8rc_nox0 = ADDItocL %32:g8rc_and_g8rc_nox0, %const.0, implicit $x2
128B	  %34:vsrprc = LXVP 0, %33:g8rc_and_g8rc_nox0 :: (load 32 from constant-pool)
144B	  %35:vsrc = COPY %34.sub_vsx1:vsrprc
160B	  undef %36.sub_vsx1:vsrprc = COPY %35:vsrc
176B	  %38:vsrc = COPY %34.sub_vsx0:vsrprc
192B	  %39:vsrprc = COPY %36:vsrprc
208B	  %39.sub_vsx0:vsrprc = COPY %38:vsrc
224B	  %40:vsrc = COPY %39.sub_vsx0:vsrprc
240B	  %41:vsrc = COPY %40:vsrc
256B	  %28:g8rc = LI8 0
272B	  %1:vsrc = LXVDSX $zero8, %28:g8rc :: (load 8 from `double* null`)
288B	  %42:vsrprc = LXVP 0, $zero8
304B	  %43:vsrc = COPY %42.sub_vsx0:vsrprc
320B	  %44:vsrc = COPY %42.sub_vsx1:vsrprc
336B	  %45:vsrc = COPY %44:vsrc
352B	  %46:vsrc = COPY %43:vsrc
368B	  %47:g8rc = LI8 -8
384B	  %5:vsrc = LXVDSX %25:g8rc_and_g8rc_nox0, %47:g8rc :: (load 8 from %ir.4)
400B	  %6:vsrc = LXVDSX $zero8, undef %48:g8rc :: (load 8 from `double* undef`)
416B	  %8:g8rc = COPY %25:g8rc_and_g8rc_nox0
432B	  %49:g8rc = LI8 1
448B	  MTCTR8loop %49:g8rc, implicit-def dead $ctr8
464B	  %50:vsrc = XXLXORz
480B	  %51:vsrc = COPY %50:vsrc
496B	  %31:vsrc = COPY %51:vsrc
512B	  %61:g8rc = LI8 512
528B	  %63:g8rc = LI8 528
544B	  %65:g8rc = LI8 56
560B	  %87:g8rc = LI8 616
576B	  %107:g8rc = LI8 704
592B	  %115:g8rc = LI8 744
608B	  %123:g8rc = LI8 784
624B	  %126:g8rc = LI8 312
640B	  %142:g8rc = LI8 792
656B	  %144:g8rc = LI8 800
672B	  %146:g8rc = LI8 808
688B	  %148:g8rc = LI8 816
704B	  %151:g8rc = LI8 344
720B	  %167:g8rc = LI8 824
736B	  %169:g8rc = LI8 832
752B	  %171:g8rc = LI8 840
768B	  %173:g8rc = LI8 848
784B	  %176:g8rc = LI8 376
800B	  %192:g8rc = LI8 856
816B	  %194:g8rc = LI8 864
832B	  %196:g8rc = LI8 880
848B	  %199:g8rc = LI8 408
864B	  %215:g8rc = LI8 904
880B	  %218:g8rc = LI8 440
896B	  %234:g8rc = LI8 920
912B	  %236:g8rc = LI8 928
928B	  %238:g8rc = LI8 936
944B	  %240:g8rc = LI8 944
960B	  %243:g8rc = LI8 472
976B	  %259:g8rc = LI8 952
992B	  %261:g8rc = LI8 960
1008B	  %263:g8rc = LI8 968
1024B	  %264:g8rc = LI8 976
1040B	  %267:g8rc = LI8 504
1056B	  %285:g8rc_and_g8rc_nox0 = COPY %28:g8rc
1072B	  %286:g8rc_and_g8rc_nox0 = IMPLICIT_DEF
1088B	  %287:vsrc = IMPLICIT_DEF
1104B	  %288:vsrc = IMPLICIT_DEF
1120B	  %289:vsrc = COPY %31:vsrc
1136B	  %290:vsrc = COPY %31:vsrc
1152B	  %291:g8rc_and_g8rc_nox0 = COPY %8:g8rc

1168B	bb.2.bb9:
	; predecessors: %bb.1, %bb.2
	  successors: %bb.2(0x80000000), %bb.3(0x00000000); %bb.2(100.00%), %bb.3(0.00%)

1184B	  %15:g8rc_and_g8rc_nox0 = COPY %291:g8rc_and_g8rc_nox0
1200B	  %14:vsrc = COPY %290:vsrc
1216B	  %13:vsrc = COPY %289:vsrc
1232B	  %12:vsrc = COPY %288:vsrc
1248B	  %11:vsrc = COPY %287:vsrc
1264B	  %10:g8rc_and_g8rc_nox0 = COPY %286:g8rc_and_g8rc_nox0
1280B	  %9:g8rc_and_g8rc_nox0 = COPY %285:g8rc_and_g8rc_nox0
1296B	  %16:g8rc = ADDI8 %15:g8rc_and_g8rc_nox0, 512
1312B	  %54:vsrc = COPY %14:vsrc
1328B	  %54:vsrc = contract nofpexcept XVMADDADP %54:vsrc(tied-def 0), %11:vsrc, %50:vsrc, implicit $rm
1344B	  %55:vsrc = COPY %13:vsrc
1360B	  %55:vsrc = contract nofpexcept XVMADDADP %55:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1376B	  %56:vsrc = COPY %12:vsrc
1392B	  %56:vsrc = contract nofpexcept XVMADDADP %56:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1408B	  %57:vsrc = COPY %54:vsrc
1424B	  %57:vsrc = contract nofpexcept XVMADDADP %57:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1440B	  %58:vsrc = COPY %55:vsrc
1456B	  %58:vsrc = contract nofpexcept XVMADDADP %58:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1472B	  %59:vsrc = COPY %56:vsrc
1488B	  %59:vsrc = contract nofpexcept XVMADDADP %59:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1504B	  %60:g8rc_and_g8rc_nox0 = ADD8 %24:g8rc, %9:g8rc_and_g8rc_nox0
1520B	  %62:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %61:g8rc :: (load 8 from %ir.i33.inc.cast)
1536B	  %64:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %63:g8rc :: (load 8 from %ir.scevgep123.cast)
1552B	  %66:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %65:g8rc
1568B	  %67:vsrc = COPY %66.sub_vsx1:vsrprc
1584B	  %68:vsrc = COPY %57:vsrc
1600B	  %68:vsrc = contract nofpexcept XVMADDADP %68:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1616B	  %70:vsrc = COPY %58:vsrc
1632B	  %70:vsrc = contract nofpexcept XVMADDADP %70:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1648B	  %71:vsrc = COPY %59:vsrc
1664B	  %71:vsrc = contract nofpexcept XVMADDADP %71:vsrc(tied-def 0), %67:vsrc, %62:vsrc, implicit $rm
1680B	  %72:vsrc = COPY %68:vsrc
1696B	  %72:vsrc = contract nofpexcept XVMADDADP %72:vsrc(tied-def 0), %41:vsrc, %50:vsrc, implicit $rm
1712B	  %73:vsrc = COPY %70:vsrc
1728B	  %73:vsrc = contract nofpexcept XVMADDADP %73:vsrc(tied-def 0), %41:vsrc, %62:vsrc, implicit $rm
1744B	  %74:vsrc = COPY %71:vsrc
1760B	  %74:vsrc = contract nofpexcept XVMADDADP %74:vsrc(tied-def 0), %64:vsrc, %50:vsrc, implicit $rm
1776B	  %75:vsrc = COPY %72:vsrc
1792B	  %75:vsrc = contract nofpexcept XVMADDADP %75:vsrc(tied-def 0), %45:vsrc, %50:vsrc, implicit $rm
1808B	  %76:vsrc = COPY %73:vsrc
1824B	  %76:vsrc = contract nofpexcept XVMADDADP %76:vsrc(tied-def 0), %45:vsrc, %64:vsrc, implicit $rm
1840B	  %77:vsrc = COPY %74:vsrc
1856B	  %77:vsrc = contract nofpexcept XVMADDADP %77:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1872B	  %78:vsrc = COPY %75:vsrc
1888B	  %78:vsrc = contract nofpexcept XVMADDADP %78:vsrc(tied-def 0), %46:vsrc, %50:vsrc, implicit $rm
1904B	  %79:vsrc = COPY %76:vsrc
1920B	  %79:vsrc = contract nofpexcept XVMADDADP %79:vsrc(tied-def 0), %46:vsrc, %50:vsrc, implicit $rm
1936B	  %80:vsrc = COPY %77:vsrc
1952B	  %80:vsrc = contract nofpexcept XVMADDADP %80:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
1968B	  %81:vsrc = COPY %78:vsrc
1984B	  %81:vsrc = contract nofpexcept XVMADDADP %81:vsrc(tied-def 0), %1:vsrc, %50:vsrc, implicit $rm
2000B	  %82:vsrc = COPY %79:vsrc
2016B	  %82:vsrc = contract nofpexcept XVMADDADP %82:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2032B	  %83:vsrc = COPY %80:vsrc
2048B	  %83:vsrc = contract nofpexcept XVMADDADP %83:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2064B	  %84:vsrc = COPY %81:vsrc
2080B	  %84:vsrc = contract nofpexcept XVMADDADP %84:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2096B	  %85:vsrc = COPY %82:vsrc
2112B	  %85:vsrc = contract nofpexcept XVMADDADP %85:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2128B	  %86:vsrc = COPY %83:vsrc
2144B	  %86:vsrc = contract nofpexcept XVMADDADP %86:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2160B	  %88:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %87:g8rc :: (load 8 from %ir.scevgep111.cast)
2176B	  %89:vsrc = COPY %84:vsrc
2192B	  %89:vsrc = contract nofpexcept XVMADDADP %89:vsrc(tied-def 0), %5:vsrc, %50:vsrc, implicit $rm
2208B	  %90:vsrc = COPY %85:vsrc
2224B	  %90:vsrc = contract nofpexcept XVMADDADP %90:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2240B	  %91:vsrc = COPY %86:vsrc
2256B	  %91:vsrc = contract nofpexcept XVMADDADP %91:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2272B	  %92:vsrc = COPY %89:vsrc
2288B	  %92:vsrc = contract nofpexcept XVMADDADP %92:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2304B	  %93:vsrc = COPY %90:vsrc
2320B	  %93:vsrc = contract nofpexcept XVMADDADP %93:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2336B	  %94:vsrc = COPY %91:vsrc
2352B	  %94:vsrc = contract nofpexcept XVMADDADP %94:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2368B	  %95:vsrc = COPY %92:vsrc
2384B	  %95:vsrc = contract nofpexcept XVMADDADP %95:vsrc(tied-def 0), %88:vsrc, %50:vsrc, implicit $rm
2400B	  %96:vsrc = COPY %93:vsrc
2416B	  %96:vsrc = contract nofpexcept XVMADDADP %96:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2432B	  %97:vsrc = COPY %94:vsrc
2448B	  %97:vsrc = contract nofpexcept XVMADDADP %97:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2464B	  %98:vsrc = COPY %95:vsrc
2480B	  %98:vsrc = contract nofpexcept XVMADDADP %98:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2496B	  %99:vsrc = COPY %96:vsrc
2512B	  %99:vsrc = contract nofpexcept XVMADDADP %99:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2528B	  %100:vsrc = COPY %97:vsrc
2544B	  %100:vsrc = contract nofpexcept XVMADDADP %100:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2560B	  %101:vsrc = COPY %98:vsrc
2576B	  %101:vsrc = contract nofpexcept XVMADDADP %101:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2592B	  %102:vsrc = COPY %99:vsrc
2608B	  %102:vsrc = contract nofpexcept XVMADDADP %102:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2624B	  %103:vsrc = COPY %100:vsrc
2640B	  %103:vsrc = contract nofpexcept XVMADDADP %103:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2656B	  %104:vsrc = COPY %101:vsrc
2672B	  %104:vsrc = contract nofpexcept XVMADDADP %104:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2688B	  %105:vsrc = COPY %102:vsrc
2704B	  %105:vsrc = contract nofpexcept XVMADDADP %105:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2720B	  %106:vsrc = COPY %103:vsrc
2736B	  %106:vsrc = contract nofpexcept XVMADDADP %106:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2752B	  %108:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %107:g8rc :: (load 8 from %ir.scevgep126.cast)
2768B	  %109:vsrc = COPY %104:vsrc
2784B	  %109:vsrc = contract nofpexcept XVMADDADP %109:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2800B	  %110:vsrc = COPY %105:vsrc
2816B	  %110:vsrc = contract nofpexcept XVMADDADP %110:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2832B	  %111:vsrc = COPY %106:vsrc
2848B	  %111:vsrc = contract nofpexcept XVMADDADP %111:vsrc(tied-def 0), %108:vsrc, %50:vsrc, implicit $rm
2864B	  %112:vsrc = COPY %109:vsrc
2880B	  %112:vsrc = contract nofpexcept XVMADDADP %112:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2896B	  %113:vsrc = COPY %110:vsrc
2912B	  %113:vsrc = contract nofpexcept XVMADDADP %113:vsrc(tied-def 0), %108:vsrc, %50:vsrc, implicit $rm
2928B	  %114:vsrc = COPY %111:vsrc
2944B	  %114:vsrc = contract nofpexcept XVMADDADP %114:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
2960B	  %116:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %115:g8rc :: (load 8 from %ir.scevgep108.cast)
2976B	  %117:vsrc = COPY %112:vsrc
2992B	  %117:vsrc = contract nofpexcept XVMADDADP %117:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
3008B	  %118:vsrc = COPY %113:vsrc
3024B	  %118:vsrc = contract nofpexcept XVMADDADP %118:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
3040B	  %119:vsrc = COPY %114:vsrc
3056B	  %119:vsrc = contract nofpexcept XVMADDADP %119:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
3072B	  %120:vsrc = COPY %117:vsrc
3088B	  %120:vsrc = contract nofpexcept XVMADDADP %120:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
3104B	  %121:vsrc = COPY %118:vsrc
3120B	  %121:vsrc = contract nofpexcept XVMADDADP %121:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
3136B	  %122:vsrc = COPY %119:vsrc
3152B	  %122:vsrc = contract nofpexcept XVMADDADP %122:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
3168B	  %124:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %123:g8rc :: (load 8 from %ir.scevgep129.cast)
3184B	  %125:vsrprc = LXVP 288, %10:g8rc_and_g8rc_nox0
3200B	  %127:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %126:g8rc
3216B	  %128:vsrc = COPY %125.sub_vsx0:vsrprc
3232B	  %129:vsrc = COPY %125.sub_vsx1:vsrprc
3248B	  %130:vsrc = COPY %127.sub_vsx0:vsrprc
3264B	  %131:vsrc = COPY %127.sub_vsx1:vsrprc
3280B	  %133:vsrc = COPY %120:vsrc
3296B	  %133:vsrc = contract nofpexcept XVMADDADP %133:vsrc(tied-def 0), %129:vsrc, %116:vsrc, implicit $rm
3312B	  %135:vsrc = COPY %121:vsrc
3328B	  %135:vsrc = contract nofpexcept XVMADDADP %135:vsrc(tied-def 0), %129:vsrc, %50:vsrc, implicit $rm
3344B	  %136:vsrc = COPY %122:vsrc
3360B	  %136:vsrc = contract nofpexcept XVMADDADP %136:vsrc(tied-def 0), %131:vsrc, %5:vsrc, implicit $rm
3376B	  %138:vsrc = COPY %133:vsrc
3392B	  %138:vsrc = contract nofpexcept XVMADDADP %138:vsrc(tied-def 0), %128:vsrc, %50:vsrc, implicit $rm
3408B	  %140:vsrc = COPY %135:vsrc
3424B	  %140:vsrc = contract nofpexcept XVMADDADP %140:vsrc(tied-def 0), %128:vsrc, %5:vsrc, implicit $rm
3440B	  %141:vsrc = COPY %136:vsrc
3456B	  %141:vsrc = contract nofpexcept XVMADDADP %141:vsrc(tied-def 0), %130:vsrc, %124:vsrc, implicit $rm
3472B	  %143:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %142:g8rc :: (load 8 from %ir.scevgep132.cast)
3488B	  %145:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %144:g8rc :: (load 8 from %ir.scevgep135.cast)
3504B	  %147:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %146:g8rc :: (load 8 from %ir.scevgep105.cast)
3520B	  %149:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %148:g8rc :: (load 8 from %ir.scevgep138.cast)
3536B	  %150:vsrprc = LXVP 320, %10:g8rc_and_g8rc_nox0
3552B	  %152:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %151:g8rc
3568B	  %153:vsrc = COPY %150.sub_vsx0:vsrprc
3584B	  %154:vsrc = COPY %150.sub_vsx1:vsrprc
3600B	  %155:vsrc = COPY %152.sub_vsx0:vsrprc
3616B	  %156:vsrc = COPY %152.sub_vsx1:vsrprc
3632B	  %158:vsrc = COPY %138:vsrc
3648B	  %158:vsrc = contract nofpexcept XVMADDADP %158:vsrc(tied-def 0), %154:vsrc, %50:vsrc, implicit $rm
3664B	  %160:vsrc = COPY %140:vsrc
3680B	  %160:vsrc = contract nofpexcept XVMADDADP %160:vsrc(tied-def 0), %154:vsrc, %124:vsrc, implicit $rm
3696B	  %161:vsrc = COPY %141:vsrc
3712B	  %161:vsrc = contract nofpexcept XVMADDADP %161:vsrc(tied-def 0), %156:vsrc, %145:vsrc, implicit $rm
3728B	  %163:vsrc = COPY %158:vsrc
3744B	  %163:vsrc = contract nofpexcept XVMADDADP %163:vsrc(tied-def 0), %153:vsrc, %143:vsrc, implicit $rm
3760B	  %165:vsrc = COPY %160:vsrc
3776B	  %165:vsrc = contract nofpexcept XVMADDADP %165:vsrc(tied-def 0), %153:vsrc, %145:vsrc, implicit $rm
3792B	  %166:vsrc = COPY %161:vsrc
3808B	  %166:vsrc = contract nofpexcept XVMADDADP %166:vsrc(tied-def 0), %155:vsrc, %149:vsrc, implicit $rm
3824B	  %168:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %167:g8rc :: (load 8 from %ir.scevgep141.cast)
3840B	  %170:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %169:g8rc :: (load 8 from %ir.scevgep144.cast)
3856B	  %172:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %171:g8rc :: (load 8 from %ir.scevgep102.cast)
3872B	  %174:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %173:g8rc :: (load 8 from %ir.scevgep147.cast)
3888B	  %175:vsrprc = LXVP 352, %10:g8rc_and_g8rc_nox0
3904B	  %177:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %176:g8rc
3920B	  %178:vsrc = COPY %175.sub_vsx0:vsrprc
3936B	  %179:vsrc = COPY %175.sub_vsx1:vsrprc
3952B	  %180:vsrc = COPY %177.sub_vsx0:vsrprc
3968B	  %181:vsrc = COPY %177.sub_vsx1:vsrprc
3984B	  %183:vsrc = COPY %163:vsrc
4000B	  %183:vsrc = contract nofpexcept XVMADDADP %183:vsrc(tied-def 0), %179:vsrc, %147:vsrc, implicit $rm
4016B	  %185:vsrc = COPY %165:vsrc
4032B	  %185:vsrc = contract nofpexcept XVMADDADP %185:vsrc(tied-def 0), %179:vsrc, %149:vsrc, implicit $rm
4048B	  %186:vsrc = COPY %166:vsrc
4064B	  %186:vsrc = contract nofpexcept XVMADDADP %186:vsrc(tied-def 0), %181:vsrc, %170:vsrc, implicit $rm
4080B	  %188:vsrc = COPY %183:vsrc
4096B	  %188:vsrc = contract nofpexcept XVMADDADP %188:vsrc(tied-def 0), %178:vsrc, %168:vsrc, implicit $rm
4112B	  %190:vsrc = COPY %185:vsrc
4128B	  %190:vsrc = contract nofpexcept XVMADDADP %190:vsrc(tied-def 0), %178:vsrc, %170:vsrc, implicit $rm
4144B	  %191:vsrc = COPY %186:vsrc
4160B	  %191:vsrc = contract nofpexcept XVMADDADP %191:vsrc(tied-def 0), %180:vsrc, %174:vsrc, implicit $rm
4176B	  %193:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %192:g8rc :: (load 8 from %ir.scevgep150.cast)
4192B	  %195:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %194:g8rc :: (load 8 from %ir.scevgep153.cast)
4208B	  %197:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %196:g8rc :: (load 8 from %ir.scevgep156.cast)
4224B	  %198:vsrprc = LXVP 384, %10:g8rc_and_g8rc_nox0
4240B	  %200:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %199:g8rc
4256B	  %201:vsrc = COPY %198.sub_vsx0:vsrprc
4272B	  %202:vsrc = COPY %198.sub_vsx1:vsrprc
4288B	  %203:vsrc = COPY %200.sub_vsx0:vsrprc
4304B	  %204:vsrc = COPY %200.sub_vsx1:vsrprc
4320B	  %206:vsrc = COPY %188:vsrc
4336B	  %206:vsrc = contract nofpexcept XVMADDADP %206:vsrc(tied-def 0), %202:vsrc, %172:vsrc, implicit $rm
4352B	  %208:vsrc = COPY %190:vsrc
4368B	  %208:vsrc = contract nofpexcept XVMADDADP %208:vsrc(tied-def 0), %202:vsrc, %174:vsrc, implicit $rm
4384B	  %209:vsrc = COPY %191:vsrc
4400B	  %209:vsrc = contract nofpexcept XVMADDADP %209:vsrc(tied-def 0), %204:vsrc, %195:vsrc, implicit $rm
4416B	  %211:vsrc = COPY %206:vsrc
4432B	  %211:vsrc = contract nofpexcept XVMADDADP %211:vsrc(tied-def 0), %201:vsrc, %193:vsrc, implicit $rm
4448B	  %213:vsrc = COPY %208:vsrc
4464B	  %213:vsrc = contract nofpexcept XVMADDADP %213:vsrc(tied-def 0), %201:vsrc, %195:vsrc, implicit $rm
4480B	  %214:vsrc = COPY %209:vsrc
4496B	  %214:vsrc = contract nofpexcept XVMADDADP %214:vsrc(tied-def 0), %203:vsrc, %197:vsrc, implicit $rm
4512B	  %216:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %215:g8rc :: (load 8 from %ir.scevgep99.cast)
4528B	  %217:vsrprc = LXVP 416, %10:g8rc_and_g8rc_nox0
4544B	  %219:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %218:g8rc
4560B	  %220:vsrc = COPY %217.sub_vsx0:vsrprc
4576B	  %221:vsrc = COPY %217.sub_vsx1:vsrprc
4592B	  %222:vsrc = COPY %219.sub_vsx0:vsrprc
4608B	  %223:vsrc = COPY %219.sub_vsx1:vsrprc
4624B	  %225:vsrc = COPY %211:vsrc
4640B	  %225:vsrc = contract nofpexcept XVMADDADP %225:vsrc(tied-def 0), %221:vsrc, %50:vsrc, implicit $rm
4656B	  %227:vsrc = COPY %213:vsrc
4672B	  %227:vsrc = contract nofpexcept XVMADDADP %227:vsrc(tied-def 0), %221:vsrc, %197:vsrc, implicit $rm
4688B	  %228:vsrc = COPY %214:vsrc
4704B	  %228:vsrc = contract nofpexcept XVMADDADP %228:vsrc(tied-def 0), %223:vsrc, %6:vsrc, implicit $rm
4720B	  %230:vsrc = COPY %225:vsrc
4736B	  %230:vsrc = contract nofpexcept XVMADDADP %230:vsrc(tied-def 0), %220:vsrc, %50:vsrc, implicit $rm
4752B	  %232:vsrc = COPY %227:vsrc
4768B	  %232:vsrc = contract nofpexcept XVMADDADP %232:vsrc(tied-def 0), %220:vsrc, %6:vsrc, implicit $rm
4784B	  %233:vsrc = COPY %228:vsrc
4800B	  %233:vsrc = contract nofpexcept XVMADDADP %233:vsrc(tied-def 0), %222:vsrc, %6:vsrc, implicit $rm
4816B	  %235:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %234:g8rc :: (load 8 from %ir.scevgep159.cast)
4832B	  %237:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %236:g8rc :: (load 8 from %ir.scevgep162.cast)
4848B	  %239:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %238:g8rc :: (load 8 from %ir.scevgep96.cast)
4864B	  %241:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %240:g8rc :: (load 8 from %ir.scevgep165.cast)
4880B	  %242:vsrprc = LXVP 448, %10:g8rc_and_g8rc_nox0
4896B	  %244:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %243:g8rc
4912B	  %245:vsrc = COPY %242.sub_vsx0:vsrprc
4928B	  %246:vsrc = COPY %242.sub_vsx1:vsrprc
4944B	  %247:vsrc = COPY %244.sub_vsx0:vsrprc
4960B	  %248:vsrc = COPY %244.sub_vsx1:vsrprc
4976B	  %250:vsrc = COPY %230:vsrc
4992B	  %250:vsrc = contract nofpexcept XVMADDADP %250:vsrc(tied-def 0), %246:vsrc, %216:vsrc, implicit $rm
5008B	  %252:vsrc = COPY %232:vsrc
5024B	  %252:vsrc = contract nofpexcept XVMADDADP %252:vsrc(tied-def 0), %246:vsrc, %6:vsrc, implicit $rm
5040B	  %253:vsrc = COPY %233:vsrc
5056B	  %253:vsrc = contract nofpexcept XVMADDADP %253:vsrc(tied-def 0), %248:vsrc, %237:vsrc, implicit $rm
5072B	  %255:vsrc = COPY %250:vsrc
5088B	  %255:vsrc = contract nofpexcept XVMADDADP %255:vsrc(tied-def 0), %245:vsrc, %235:vsrc, implicit $rm
5104B	  %257:vsrc = COPY %252:vsrc
5120B	  %257:vsrc = contract nofpexcept XVMADDADP %257:vsrc(tied-def 0), %245:vsrc, %237:vsrc, implicit $rm
5136B	  %258:vsrc = COPY %253:vsrc
5152B	  %258:vsrc = contract nofpexcept XVMADDADP %258:vsrc(tied-def 0), %247:vsrc, %241:vsrc, implicit $rm
5168B	  %260:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %259:g8rc :: (load 8 from %ir.scevgep117.cast)
5184B	  %262:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %261:g8rc :: (load 8 from %ir.scevgep114.cast)
5200B	  %17:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %263:g8rc :: (load 8 from %ir.scevgep93.cast)
5216B	  %265:vsrc = LXVDSX %15:g8rc_and_g8rc_nox0, %264:g8rc :: (load 8 from %ir.uglygep8990.cast)
5232B	  %266:vsrprc = LXVP 480, %10:g8rc_and_g8rc_nox0
5248B	  %268:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %267:g8rc
5264B	  %269:vsrc = COPY %266.sub_vsx0:vsrprc
5280B	  %270:vsrc = COPY %268.sub_vsx0:vsrprc
5296B	  %271:vsrc = COPY %255:vsrc
5312B	  %271:vsrc = contract nofpexcept XVMADDADP %271:vsrc(tied-def 0), %239:vsrc, %50:vsrc, implicit $rm
5328B	  %272:vsrc = COPY %257:vsrc
5344B	  %272:vsrc = contract nofpexcept XVMADDADP %272:vsrc(tied-def 0), %241:vsrc, %50:vsrc, implicit $rm
5360B	  %273:vsrc = COPY %258:vsrc
5376B	  %273:vsrc = contract nofpexcept XVMADDADP %273:vsrc(tied-def 0), %262:vsrc, %50:vsrc, implicit $rm
5392B	  %18:vsrc = COPY %271:vsrc
5408B	  %18:vsrc = contract nofpexcept XVMADDADP %18:vsrc(tied-def 0), %269:vsrc, %260:vsrc, implicit $rm
5424B	  %19:vsrc = COPY %272:vsrc
5440B	  %19:vsrc = contract nofpexcept XVMADDADP %19:vsrc(tied-def 0), %269:vsrc, %262:vsrc, implicit $rm
5456B	  %20:vsrc = COPY %273:vsrc
5472B	  %20:vsrc = contract nofpexcept XVMADDADP %20:vsrc(tied-def 0), %270:vsrc, %265:vsrc, implicit $rm
5488B	  %21:g8rc = nsw ADDI8 %10:g8rc_and_g8rc_nox0, 512
5504B	  %22:g8rc = ADDI8 %9:g8rc_and_g8rc_nox0, 512
5520B	  %285:g8rc_and_g8rc_nox0 = COPY %22:g8rc
5536B	  %286:g8rc_and_g8rc_nox0 = COPY %21:g8rc
5552B	  %287:vsrc = COPY %17:vsrc
5568B	  %288:vsrc = COPY %20:vsrc
5584B	  %289:vsrc = COPY %19:vsrc
5600B	  %290:vsrc = COPY %18:vsrc
5616B	  %291:g8rc_and_g8rc_nox0 = COPY %16:g8rc
5632B	  BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8
5648B	  B %bb.3

5664B	bb.3.bb421:
	; predecessors: %bb.0, %bb.2

5680B	  %276:vsrc = XXLXORz
5696B	  %278:vrrc = COPY %276:vsrc
5712B	  %278:vrrc = XXSPLTI32DX %278:vrrc(tied-def 0), 0, 2146959360
5728B	  undef %283.sub_vsx0:vsrprc = COPY %278:vrrc
5744B	  STXVP %283:vsrprc, 0, undef %284:g8rc_and_g8rc_nox0

# End machine code for function test.

********** SIMPLE REGISTER COALESCING **********
********** Function: test
********** JOINING INTERVALS ***********
bb9:
1184B	%15:g8rc_and_g8rc_nox0 = COPY %291:g8rc_and_g8rc_nox0
	Considering merging to G8RC_and_G8RC_NOX0 with %15 in %291
		RHS = %15 [1184r,5216r:0)  0 at 1184r weight:0.000000e+00
		LHS = %291 [1152r,1168B:0)[1168B,1184r:2)[5616r,5664B:1)  0 at 1152r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
		merge %15:0 at 1184r into %291:2 at 1168B --> @1168B
		erased:	1184r	%15:g8rc_and_g8rc_nox0 = COPY %291:g8rc_and_g8rc_nox0
AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 $x31 ]
		updated: 1296B	%16:g8rc = ADDI8 %291:g8rc_and_g8rc_nox0, 512
		updated: 1520B	%62:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %61:g8rc :: (load 8 from %ir.i33.inc.cast)
		updated: 1536B	%64:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %63:g8rc :: (load 8 from %ir.scevgep123.cast)
		updated: 2160B	%88:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %87:g8rc :: (load 8 from %ir.scevgep111.cast)
		updated: 2752B	%108:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %107:g8rc :: (load 8 from %ir.scevgep126.cast)
		updated: 2960B	%116:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %115:g8rc :: (load 8 from %ir.scevgep108.cast)
		updated: 3168B	%124:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %123:g8rc :: (load 8 from %ir.scevgep129.cast)
		updated: 3472B	%143:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %142:g8rc :: (load 8 from %ir.scevgep132.cast)
		updated: 3488B	%145:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %144:g8rc :: (load 8 from %ir.scevgep135.cast)
		updated: 3504B	%147:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %146:g8rc :: (load 8 from %ir.scevgep105.cast)
		updated: 3520B	%149:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %148:g8rc :: (load 8 from %ir.scevgep138.cast)
		updated: 3824B	%168:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %167:g8rc :: (load 8 from %ir.scevgep141.cast)
		updated: 3840B	%170:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %169:g8rc :: (load 8 from %ir.scevgep144.cast)
		updated: 3856B	%172:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %171:g8rc :: (load 8 from %ir.scevgep102.cast)
		updated: 3872B	%174:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %173:g8rc :: (load 8 from %ir.scevgep147.cast)
		updated: 4176B	%193:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %192:g8rc :: (load 8 from %ir.scevgep150.cast)
		updated: 4192B	%195:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %194:g8rc :: (load 8 from %ir.scevgep153.cast)
		updated: 4208B	%197:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %196:g8rc :: (load 8 from %ir.scevgep156.cast)
		updated: 4512B	%216:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %215:g8rc :: (load 8 from %ir.scevgep99.cast)
		updated: 4816B	%235:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %234:g8rc :: (load 8 from %ir.scevgep159.cast)
		updated: 4832B	%237:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %236:g8rc :: (load 8 from %ir.scevgep162.cast)
		updated: 4848B	%239:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %238:g8rc :: (load 8 from %ir.scevgep96.cast)
		updated: 4864B	%241:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %240:g8rc :: (load 8 from %ir.scevgep165.cast)
		updated: 5168B	%260:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %259:g8rc :: (load 8 from %ir.scevgep117.cast)
		updated: 5184B	%262:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %261:g8rc :: (load 8 from %ir.scevgep114.cast)
		updated: 5200B	%17:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %263:g8rc :: (load 8 from %ir.scevgep93.cast)
		updated: 5216B	%265:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %264:g8rc :: (load 8 from %ir.uglygep8990.cast)
	Success: %15 -> %291
	Result = %291 [1152r,1168B:0)[1168B,5216r:2)[5616r,5664B:1)  0 at 1152r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
1200B	%14:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %14 in %290
		RHS = %14 [1200r,1312r:0)  0 at 1200r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1200r:2)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi weight:0.000000e+00
		merge %14:0 at 1200r into %290:2 at 1168B --> @1168B
		erased:	1200r	%14:vsrc = COPY %290:vsrc
AllocationOrder(VSRC) = [ $vsl0 $vsl1 $vsl2 $vsl3 $vsl4 $vsl5 $vsl6 $vsl7 $vsl8 $vsl9 $vsl10 $vsl11 $vsl12 $vsl13 $v2 $v3 $v4 $v5 $v0 $v1 $v6 $v7 $v8 $v9 $v10 $v11 $v12 $v13 $v14 $v15 $v16 $v17 $v18 $v19 $vsl31 $vsl30 $vsl29 $vsl28 $vsl27 $vsl26 $vsl25 $vsl24 $vsl23 $vsl22 $vsl21 $vsl20 $vsl19 $vsl18 $vsl17 $vsl16 $vsl15 $vsl14 $v31 $v30 $v29 $v28 $v27 $v26 $v25 $v24 $v23 $v22 $v21 $v20 ]
		updated: 1312B	%54:vsrc = COPY %290:vsrc
	Success: %14 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1312r:2)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi weight:0.000000e+00
1216B	%13:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %13 in %289
		RHS = %13 [1216r,1344r:0)  0 at 1216r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1216r:2)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi weight:0.000000e+00
		merge %13:0 at 1216r into %289:2 at 1168B --> @1168B
		erased:	1216r	%13:vsrc = COPY %289:vsrc
		updated: 1344B	%55:vsrc = COPY %289:vsrc
	Success: %13 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1344r:2)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi weight:0.000000e+00
1232B	%12:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %12 in %288
		RHS = %12 [1232r,1376r:0)  0 at 1232r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1232r:2)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi weight:0.000000e+00
		merge %12:0 at 1232r into %288:2 at 1168B --> @1168B
		erased:	1232r	%12:vsrc = COPY %288:vsrc
		updated: 1376B	%56:vsrc = COPY %288:vsrc
	Success: %12 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1376r:2)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi weight:0.000000e+00
1248B	%11:vsrc = COPY %287:vsrc
	Considering merging to VSRC with %11 in %287
		RHS = %11 [1248r,1328r:0)  0 at 1248r weight:0.000000e+00
		LHS = %287 [1088r,1168B:0)[1168B,1248r:2)[5552r,5664B:1)  0 at 1088r 1 at 5552r 2 at 1168B-phi weight:0.000000e+00
		merge %11:0 at 1248r into %287:2 at 1168B --> @1168B
		erased:	1248r	%11:vsrc = COPY %287:vsrc
		updated: 1328B	%54:vsrc = contract nofpexcept XVMADDADP %54:vsrc(tied-def 0), %287:vsrc, %50:vsrc, implicit $rm
	Success: %11 -> %287
	Result = %287 [1088r,1168B:0)[1168B,1328r:2)[5552r,5664B:1)  0 at 1088r 1 at 5552r 2 at 1168B-phi weight:0.000000e+00
1264B	%10:g8rc_and_g8rc_nox0 = COPY %286:g8rc_and_g8rc_nox0
	Considering merging to G8RC_and_G8RC_NOX0 with %10 in %286
		RHS = %10 [1264r,5488r:0)  0 at 1264r weight:0.000000e+00
		LHS = %286 [1072r,1168B:0)[1168B,1264r:2)[5536r,5664B:1)  0 at 1072r 1 at 5536r 2 at 1168B-phi weight:0.000000e+00
		merge %10:0 at 1264r into %286:2 at 1168B --> @1168B
		erased:	1264r	%10:g8rc_and_g8rc_nox0 = COPY %286:g8rc_and_g8rc_nox0
		updated: 3184B	%125:vsrprc = LXVP 288, %286:g8rc_and_g8rc_nox0
		updated: 3536B	%150:vsrprc = LXVP 320, %286:g8rc_and_g8rc_nox0
		updated: 3888B	%175:vsrprc = LXVP 352, %286:g8rc_and_g8rc_nox0
		updated: 4224B	%198:vsrprc = LXVP 384, %286:g8rc_and_g8rc_nox0
		updated: 4528B	%217:vsrprc = LXVP 416, %286:g8rc_and_g8rc_nox0
		updated: 4880B	%242:vsrprc = LXVP 448, %286:g8rc_and_g8rc_nox0
		updated: 5232B	%266:vsrprc = LXVP 480, %286:g8rc_and_g8rc_nox0
		updated: 5488B	%21:g8rc = nsw ADDI8 %286:g8rc_and_g8rc_nox0, 512
	Success: %10 -> %286
	Result = %286 [1072r,1168B:0)[1168B,5488r:2)[5536r,5664B:1)  0 at 1072r 1 at 5536r 2 at 1168B-phi weight:0.000000e+00
1280B	%9:g8rc_and_g8rc_nox0 = COPY %285:g8rc_and_g8rc_nox0
	Considering merging to G8RC_and_G8RC_NOX0 with %9 in %285
		RHS = %9 [1280r,5504r:0)  0 at 1280r weight:0.000000e+00
		LHS = %285 [1056r,1168B:0)[1168B,1280r:2)[5520r,5664B:1)  0 at 1056r 1 at 5520r 2 at 1168B-phi weight:0.000000e+00
		merge %9:0 at 1280r into %285:2 at 1168B --> @1168B
		erased:	1280r	%9:g8rc_and_g8rc_nox0 = COPY %285:g8rc_and_g8rc_nox0
		updated: 5504B	%22:g8rc = ADDI8 %285:g8rc_and_g8rc_nox0, 512
		updated: 1504B	%60:g8rc_and_g8rc_nox0 = ADD8 %24:g8rc, %285:g8rc_and_g8rc_nox0
	Success: %9 -> %285
	Result = %285 [1056r,1168B:0)[1168B,5504r:2)[5520r,5664B:1)  0 at 1056r 1 at 5520r 2 at 1168B-phi weight:0.000000e+00
1312B	%54:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %54 in %290
		RHS = %54 [1312r,1328r:0)[1328r,1408r:1)  0 at 1312r 1 at 1328r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1312r:2)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi weight:0.000000e+00
		merge %54:0 at 1312r into %290:2 at 1168B --> @1168B
		erased:	1312r	%54:vsrc = COPY %290:vsrc
		updated: 1328B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %287:vsrc, %50:vsrc, implicit $rm
		updated: 1408B	%57:vsrc = COPY %290:vsrc
	Success: %54 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1408r:3)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r weight:0.000000e+00
1344B	%55:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %55 in %289
		RHS = %55 [1344r,1360r:0)[1360r,1440r:1)  0 at 1344r 1 at 1360r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1344r:2)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi weight:0.000000e+00
		merge %55:0 at 1344r into %289:2 at 1168B --> @1168B
		erased:	1344r	%55:vsrc = COPY %289:vsrc
		updated: 1360B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1440B	%58:vsrc = COPY %289:vsrc
	Success: %55 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1440r:3)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r weight:0.000000e+00
1376B	%56:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %56 in %288
		RHS = %56 [1376r,1392r:0)[1392r,1472r:1)  0 at 1376r 1 at 1392r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1376r:2)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi weight:0.000000e+00
		merge %56:0 at 1376r into %288:2 at 1168B --> @1168B
		erased:	1376r	%56:vsrc = COPY %288:vsrc
		updated: 1392B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1472B	%59:vsrc = COPY %288:vsrc
	Success: %56 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1472r:3)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r weight:0.000000e+00
1408B	%57:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %57 in %290
		RHS = %57 [1408r,1424r:0)[1424r,1584r:1)  0 at 1408r 1 at 1424r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1408r:3)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r weight:0.000000e+00
		merge %57:0 at 1408r into %290:3 at 1328r --> @1328r
		erased:	1408r	%57:vsrc = COPY %290:vsrc
		updated: 1424B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1584B	%68:vsrc = COPY %290:vsrc
	Success: %57 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1584r:4)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r weight:0.000000e+00
1440B	%58:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %58 in %289
		RHS = %58 [1440r,1456r:0)[1456r,1616r:1)  0 at 1440r 1 at 1456r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1440r:3)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r weight:0.000000e+00
		merge %58:0 at 1440r into %289:3 at 1360r --> @1360r
		erased:	1440r	%58:vsrc = COPY %289:vsrc
		updated: 1456B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1616B	%70:vsrc = COPY %289:vsrc
	Success: %58 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1616r:4)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r weight:0.000000e+00
1472B	%59:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %59 in %288
		RHS = %59 [1472r,1488r:0)[1488r,1648r:1)  0 at 1472r 1 at 1488r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1472r:3)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r weight:0.000000e+00
		merge %59:0 at 1472r into %288:3 at 1392r --> @1392r
		erased:	1472r	%59:vsrc = COPY %288:vsrc
		updated: 1488B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1648B	%71:vsrc = COPY %288:vsrc
	Success: %59 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1648r:4)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r weight:0.000000e+00
1568B	%67:vsrc = COPY %66.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %67 in %66:sub_vsx1
		RHS = %67 [1568r,1664r:0)  0 at 1568r weight:0.000000e+00
		LHS = %66 [1552r,1568r:0)  0 at 1552r L0000000000000040 [1552r,1568r:0)  0 at 1552r L0000000000000002 [1552r,1552d:0)  0 at 1552r weight:0.000000e+00
		merge %67:0 at 1568r into %66:0 at 1552r --> @1552r
		LHST = %66 %66 [1552r,1568r:0)  0 at 1552r L0000000000000040 [1552r,1568r:0)  0 at 1552r L0000000000000002 [1552r,1552d:0)  0 at 1552r weight:0.000000e+00
		merge %67:0 at 1568r into %66:0 at 1552r --> @1552r
		joined lanes: 0000000000000040 [1552r,1664r:0)  0 at 1552r
	Joined SubRanges %66 [1552r,1568r:0)  0 at 1552r L0000000000000040 [1552r,1664r:0)  0 at 1552r L0000000000000002 [1552r,1552d:0)  0 at 1552r weight:0.000000e+00
		Expecting instruction removal at 1568r
		erased:	1568r	%67:vsrc = COPY %66.sub_vsx1:vsrprc
AllocationOrder(VSRpRC) = [ $vsrp0 $vsrp1 $vsrp2 $vsrp3 $vsrp4 $vsrp5 $vsrp6 $vsrp17 $vsrp18 $vsrp16 $vsrp19 $vsrp20 $vsrp21 $vsrp22 $vsrp23 $vsrp24 $vsrp25 $vsrp15 $vsrp14 $vsrp13 $vsrp12 $vsrp11 $vsrp10 $vsrp9 $vsrp8 $vsrp7 $vsrp31 $vsrp30 $vsrp29 $vsrp28 $vsrp27 $vsrp26 ]
		updated: 1664B	%71:vsrc = contract nofpexcept XVMADDADP %71:vsrc(tied-def 0), %66.sub_vsx1:vsrprc, %62:vsrc, implicit $rm
	Success: %67:sub_vsx1 -> %66
	Result = %66 [1552r,1664r:0)  0 at 1552r L0000000000000040 [1552r,1664r:0)  0 at 1552r L0000000000000002 [1552r,1552d:0)  0 at 1552r weight:0.000000e+00
1584B	%68:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %68 in %290
		RHS = %68 [1584r,1600r:0)[1600r,1680r:1)  0 at 1584r 1 at 1600r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1584r:4)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r weight:0.000000e+00
		merge %68:0 at 1584r into %290:4 at 1424r --> @1424r
		erased:	1584r	%68:vsrc = COPY %290:vsrc
		updated: 1600B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1680B	%72:vsrc = COPY %290:vsrc
	Success: %68 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1680r:5)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r weight:0.000000e+00
1616B	%70:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %70 in %289
		RHS = %70 [1616r,1632r:0)[1632r,1712r:1)  0 at 1616r 1 at 1632r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1616r:4)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r weight:0.000000e+00
		merge %70:0 at 1616r into %289:4 at 1456r --> @1456r
		erased:	1616r	%70:vsrc = COPY %289:vsrc
		updated: 1632B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1712B	%73:vsrc = COPY %289:vsrc
	Success: %70 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1712r:5)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r weight:0.000000e+00
1648B	%71:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %71 in %288
		RHS = %71 [1648r,1664r:0)[1664r,1744r:1)  0 at 1648r 1 at 1664r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1648r:4)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r weight:0.000000e+00
		merge %71:0 at 1648r into %288:4 at 1488r --> @1488r
		erased:	1648r	%71:vsrc = COPY %288:vsrc
		updated: 1664B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %66.sub_vsx1:vsrprc, %62:vsrc, implicit $rm
		updated: 1744B	%74:vsrc = COPY %288:vsrc
	Success: %71 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1744r:5)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r weight:0.000000e+00
1680B	%72:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %72 in %290
		RHS = %72 [1680r,1696r:0)[1696r,1776r:1)  0 at 1680r 1 at 1696r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1680r:5)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r weight:0.000000e+00
		merge %72:0 at 1680r into %290:5 at 1600r --> @1600r
		erased:	1680r	%72:vsrc = COPY %290:vsrc
		updated: 1696B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %41:vsrc, %50:vsrc, implicit $rm
		updated: 1776B	%75:vsrc = COPY %290:vsrc
	Success: %72 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1776r:6)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r weight:0.000000e+00
1712B	%73:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %73 in %289
		RHS = %73 [1712r,1728r:0)[1728r,1808r:1)  0 at 1712r 1 at 1728r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1712r:5)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r weight:0.000000e+00
		merge %73:0 at 1712r into %289:5 at 1632r --> @1632r
		erased:	1712r	%73:vsrc = COPY %289:vsrc
		updated: 1728B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %41:vsrc, %62:vsrc, implicit $rm
		updated: 1808B	%76:vsrc = COPY %289:vsrc
	Success: %73 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1808r:6)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r weight:0.000000e+00
1744B	%74:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %74 in %288
		RHS = %74 [1744r,1760r:0)[1760r,1840r:1)  0 at 1744r 1 at 1760r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1744r:5)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r weight:0.000000e+00
		merge %74:0 at 1744r into %288:5 at 1664r --> @1664r
		erased:	1744r	%74:vsrc = COPY %288:vsrc
		updated: 1760B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %64:vsrc, %50:vsrc, implicit $rm
		updated: 1840B	%77:vsrc = COPY %288:vsrc
	Success: %74 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1840r:6)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r weight:0.000000e+00
1776B	%75:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %75 in %290
		RHS = %75 [1776r,1792r:0)[1792r,1872r:1)  0 at 1776r 1 at 1792r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1776r:6)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r weight:0.000000e+00
		merge %75:0 at 1776r into %290:6 at 1696r --> @1696r
		erased:	1776r	%75:vsrc = COPY %290:vsrc
		updated: 1792B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %45:vsrc, %50:vsrc, implicit $rm
		updated: 1872B	%78:vsrc = COPY %290:vsrc
	Success: %75 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1872r:7)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r weight:0.000000e+00
1808B	%76:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %76 in %289
		RHS = %76 [1808r,1824r:0)[1824r,1904r:1)  0 at 1808r 1 at 1824r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1808r:6)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r weight:0.000000e+00
		merge %76:0 at 1808r into %289:6 at 1728r --> @1728r
		erased:	1808r	%76:vsrc = COPY %289:vsrc
		updated: 1824B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %45:vsrc, %64:vsrc, implicit $rm
		updated: 1904B	%79:vsrc = COPY %289:vsrc
	Success: %76 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1904r:7)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r weight:0.000000e+00
1840B	%77:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %77 in %288
		RHS = %77 [1840r,1856r:0)[1856r,1936r:1)  0 at 1840r 1 at 1856r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1840r:6)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r weight:0.000000e+00
		merge %77:0 at 1840r into %288:6 at 1760r --> @1760r
		erased:	1840r	%77:vsrc = COPY %288:vsrc
		updated: 1856B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 1936B	%80:vsrc = COPY %288:vsrc
	Success: %77 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1936r:7)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r weight:0.000000e+00
1872B	%78:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %78 in %290
		RHS = %78 [1872r,1888r:0)[1888r,1968r:1)  0 at 1872r 1 at 1888r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1872r:7)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r weight:0.000000e+00
		merge %78:0 at 1872r into %290:7 at 1792r --> @1792r
		erased:	1872r	%78:vsrc = COPY %290:vsrc
		updated: 1888B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %46:vsrc, %50:vsrc, implicit $rm
		updated: 1968B	%81:vsrc = COPY %290:vsrc
	Success: %78 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1968r:8)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r weight:0.000000e+00
1904B	%79:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %79 in %289
		RHS = %79 [1904r,1920r:0)[1920r,2000r:1)  0 at 1904r 1 at 1920r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1904r:7)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r weight:0.000000e+00
		merge %79:0 at 1904r into %289:7 at 1824r --> @1824r
		erased:	1904r	%79:vsrc = COPY %289:vsrc
		updated: 1920B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %46:vsrc, %50:vsrc, implicit $rm
		updated: 2000B	%82:vsrc = COPY %289:vsrc
	Success: %79 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2000r:8)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r weight:0.000000e+00
1936B	%80:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %80 in %288
		RHS = %80 [1936r,1952r:0)[1952r,2032r:1)  0 at 1936r 1 at 1952r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1936r:7)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r weight:0.000000e+00
		merge %80:0 at 1936r into %288:7 at 1856r --> @1856r
		erased:	1936r	%80:vsrc = COPY %288:vsrc
		updated: 1952B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2032B	%83:vsrc = COPY %288:vsrc
	Success: %80 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2032r:8)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r weight:0.000000e+00
1968B	%81:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %81 in %290
		RHS = %81 [1968r,1984r:0)[1984r,2064r:1)  0 at 1968r 1 at 1984r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1968r:8)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r weight:0.000000e+00
		merge %81:0 at 1968r into %290:8 at 1888r --> @1888r
		erased:	1968r	%81:vsrc = COPY %290:vsrc
		updated: 1984B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %1:vsrc, %50:vsrc, implicit $rm
		updated: 2064B	%84:vsrc = COPY %290:vsrc
	Success: %81 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2064r:9)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r weight:0.000000e+00
2000B	%82:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %82 in %289
		RHS = %82 [2000r,2016r:0)[2016r,2096r:1)  0 at 2000r 1 at 2016r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2000r:8)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r weight:0.000000e+00
		merge %82:0 at 2000r into %289:8 at 1920r --> @1920r
		erased:	2000r	%82:vsrc = COPY %289:vsrc
		updated: 2016B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2096B	%85:vsrc = COPY %289:vsrc
	Success: %82 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2096r:9)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r weight:0.000000e+00
2032B	%83:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %83 in %288
		RHS = %83 [2032r,2048r:0)[2048r,2128r:1)  0 at 2032r 1 at 2048r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2032r:8)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r weight:0.000000e+00
		merge %83:0 at 2032r into %288:8 at 1952r --> @1952r
		erased:	2032r	%83:vsrc = COPY %288:vsrc
		updated: 2048B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2128B	%86:vsrc = COPY %288:vsrc
	Success: %83 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2128r:9)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r weight:0.000000e+00
2064B	%84:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %84 in %290
		RHS = %84 [2064r,2080r:0)[2080r,2176r:1)  0 at 2064r 1 at 2080r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2064r:9)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r weight:0.000000e+00
		merge %84:0 at 2064r into %290:9 at 1984r --> @1984r
		erased:	2064r	%84:vsrc = COPY %290:vsrc
		updated: 2080B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2176B	%89:vsrc = COPY %290:vsrc
	Success: %84 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2176r:10)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r weight:0.000000e+00
2096B	%85:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %85 in %289
		RHS = %85 [2096r,2112r:0)[2112r,2208r:1)  0 at 2096r 1 at 2112r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2096r:9)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r weight:0.000000e+00
		merge %85:0 at 2096r into %289:9 at 2016r --> @2016r
		erased:	2096r	%85:vsrc = COPY %289:vsrc
		updated: 2112B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2208B	%90:vsrc = COPY %289:vsrc
	Success: %85 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2208r:10)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r weight:0.000000e+00
2128B	%86:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %86 in %288
		RHS = %86 [2128r,2144r:0)[2144r,2240r:1)  0 at 2128r 1 at 2144r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2128r:9)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r weight:0.000000e+00
		merge %86:0 at 2128r into %288:9 at 2048r --> @2048r
		erased:	2128r	%86:vsrc = COPY %288:vsrc
		updated: 2144B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2240B	%91:vsrc = COPY %288:vsrc
	Success: %86 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2240r:10)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r weight:0.000000e+00
2176B	%89:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %89 in %290
		RHS = %89 [2176r,2192r:0)[2192r,2272r:1)  0 at 2176r 1 at 2192r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2176r:10)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r weight:0.000000e+00
		merge %89:0 at 2176r into %290:10 at 2080r --> @2080r
		erased:	2176r	%89:vsrc = COPY %290:vsrc
		updated: 2192B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %5:vsrc, %50:vsrc, implicit $rm
		updated: 2272B	%92:vsrc = COPY %290:vsrc
	Success: %89 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2272r:11)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r weight:0.000000e+00
2208B	%90:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %90 in %289
		RHS = %90 [2208r,2224r:0)[2224r,2304r:1)  0 at 2208r 1 at 2224r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2208r:10)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r weight:0.000000e+00
		merge %90:0 at 2208r into %289:10 at 2112r --> @2112r
		erased:	2208r	%90:vsrc = COPY %289:vsrc
		updated: 2224B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2304B	%93:vsrc = COPY %289:vsrc
	Success: %90 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2304r:11)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r weight:0.000000e+00
2240B	%91:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %91 in %288
		RHS = %91 [2240r,2256r:0)[2256r,2336r:1)  0 at 2240r 1 at 2256r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2240r:10)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r weight:0.000000e+00
		merge %91:0 at 2240r into %288:10 at 2144r --> @2144r
		erased:	2240r	%91:vsrc = COPY %288:vsrc
		updated: 2256B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2336B	%94:vsrc = COPY %288:vsrc
	Success: %91 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2336r:11)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r weight:0.000000e+00
2272B	%92:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %92 in %290
		RHS = %92 [2272r,2288r:0)[2288r,2368r:1)  0 at 2272r 1 at 2288r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2272r:11)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r weight:0.000000e+00
		merge %92:0 at 2272r into %290:11 at 2192r --> @2192r
		erased:	2272r	%92:vsrc = COPY %290:vsrc
		updated: 2288B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2368B	%95:vsrc = COPY %290:vsrc
	Success: %92 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2368r:12)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r weight:0.000000e+00
2304B	%93:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %93 in %289
		RHS = %93 [2304r,2320r:0)[2320r,2400r:1)  0 at 2304r 1 at 2320r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2304r:11)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r weight:0.000000e+00
		merge %93:0 at 2304r into %289:11 at 2224r --> @2224r
		erased:	2304r	%93:vsrc = COPY %289:vsrc
		updated: 2320B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2400B	%96:vsrc = COPY %289:vsrc
	Success: %93 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2400r:12)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r weight:0.000000e+00
2336B	%94:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %94 in %288
		RHS = %94 [2336r,2352r:0)[2352r,2432r:1)  0 at 2336r 1 at 2352r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2336r:11)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r weight:0.000000e+00
		merge %94:0 at 2336r into %288:11 at 2256r --> @2256r
		erased:	2336r	%94:vsrc = COPY %288:vsrc
		updated: 2352B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2432B	%97:vsrc = COPY %288:vsrc
	Success: %94 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2432r:12)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r weight:0.000000e+00
2368B	%95:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %95 in %290
		RHS = %95 [2368r,2384r:0)[2384r,2464r:1)  0 at 2368r 1 at 2384r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2368r:12)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r weight:0.000000e+00
		merge %95:0 at 2368r into %290:12 at 2288r --> @2288r
		erased:	2368r	%95:vsrc = COPY %290:vsrc
		updated: 2384B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %88:vsrc, %50:vsrc, implicit $rm
		updated: 2464B	%98:vsrc = COPY %290:vsrc
	Success: %95 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2464r:13)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r weight:0.000000e+00
2400B	%96:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %96 in %289
		RHS = %96 [2400r,2416r:0)[2416r,2496r:1)  0 at 2400r 1 at 2416r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2400r:12)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r weight:0.000000e+00
		merge %96:0 at 2400r into %289:12 at 2320r --> @2320r
		erased:	2400r	%96:vsrc = COPY %289:vsrc
		updated: 2416B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2496B	%99:vsrc = COPY %289:vsrc
	Success: %96 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2496r:13)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r weight:0.000000e+00
2432B	%97:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %97 in %288
		RHS = %97 [2432r,2448r:0)[2448r,2528r:1)  0 at 2432r 1 at 2448r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2432r:12)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r weight:0.000000e+00
		merge %97:0 at 2432r into %288:12 at 2352r --> @2352r
		erased:	2432r	%97:vsrc = COPY %288:vsrc
		updated: 2448B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2528B	%100:vsrc = COPY %288:vsrc
	Success: %97 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2528r:13)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r weight:0.000000e+00
2464B	%98:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %98 in %290
		RHS = %98 [2464r,2480r:0)[2480r,2560r:1)  0 at 2464r 1 at 2480r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2464r:13)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r weight:0.000000e+00
		merge %98:0 at 2464r into %290:13 at 2384r --> @2384r
		erased:	2464r	%98:vsrc = COPY %290:vsrc
		updated: 2480B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2560B	%101:vsrc = COPY %290:vsrc
	Success: %98 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2560r:14)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r weight:0.000000e+00
2496B	%99:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %99 in %289
		RHS = %99 [2496r,2512r:0)[2512r,2592r:1)  0 at 2496r 1 at 2512r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2496r:13)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r weight:0.000000e+00
		merge %99:0 at 2496r into %289:13 at 2416r --> @2416r
		erased:	2496r	%99:vsrc = COPY %289:vsrc
		updated: 2512B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2592B	%102:vsrc = COPY %289:vsrc
	Success: %99 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2592r:14)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r weight:0.000000e+00
2528B	%100:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %100 in %288
		RHS = %100 [2528r,2544r:0)[2544r,2624r:1)  0 at 2528r 1 at 2544r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2528r:13)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r weight:0.000000e+00
		merge %100:0 at 2528r into %288:13 at 2448r --> @2448r
		erased:	2528r	%100:vsrc = COPY %288:vsrc
		updated: 2544B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2624B	%103:vsrc = COPY %288:vsrc
	Success: %100 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2624r:14)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r weight:0.000000e+00
2560B	%101:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %101 in %290
		RHS = %101 [2560r,2576r:0)[2576r,2656r:1)  0 at 2560r 1 at 2576r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2560r:14)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r weight:0.000000e+00
		merge %101:0 at 2560r into %290:14 at 2480r --> @2480r
		erased:	2560r	%101:vsrc = COPY %290:vsrc
		updated: 2576B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2656B	%104:vsrc = COPY %290:vsrc
	Success: %101 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2656r:15)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r weight:0.000000e+00
2592B	%102:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %102 in %289
		RHS = %102 [2592r,2608r:0)[2608r,2688r:1)  0 at 2592r 1 at 2608r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2592r:14)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r weight:0.000000e+00
		merge %102:0 at 2592r into %289:14 at 2512r --> @2512r
		erased:	2592r	%102:vsrc = COPY %289:vsrc
		updated: 2608B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2688B	%105:vsrc = COPY %289:vsrc
	Success: %102 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2688r:15)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r weight:0.000000e+00
2624B	%103:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %103 in %288
		RHS = %103 [2624r,2640r:0)[2640r,2720r:1)  0 at 2624r 1 at 2640r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2624r:14)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r weight:0.000000e+00
		merge %103:0 at 2624r into %288:14 at 2544r --> @2544r
		erased:	2624r	%103:vsrc = COPY %288:vsrc
		updated: 2640B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2720B	%106:vsrc = COPY %288:vsrc
	Success: %103 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2720r:15)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r weight:0.000000e+00
2656B	%104:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %104 in %290
		RHS = %104 [2656r,2672r:0)[2672r,2768r:1)  0 at 2656r 1 at 2672r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2656r:15)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r weight:0.000000e+00
		merge %104:0 at 2656r into %290:15 at 2576r --> @2576r
		erased:	2656r	%104:vsrc = COPY %290:vsrc
		updated: 2672B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2768B	%109:vsrc = COPY %290:vsrc
	Success: %104 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2768r:16)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r weight:0.000000e+00
2688B	%105:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %105 in %289
		RHS = %105 [2688r,2704r:0)[2704r,2800r:1)  0 at 2688r 1 at 2704r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2688r:15)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r weight:0.000000e+00
		merge %105:0 at 2688r into %289:15 at 2608r --> @2608r
		erased:	2688r	%105:vsrc = COPY %289:vsrc
		updated: 2704B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2800B	%110:vsrc = COPY %289:vsrc
	Success: %105 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2800r:16)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r weight:0.000000e+00
2720B	%106:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %106 in %288
		RHS = %106 [2720r,2736r:0)[2736r,2832r:1)  0 at 2720r 1 at 2736r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2720r:15)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r weight:0.000000e+00
		merge %106:0 at 2720r into %288:15 at 2640r --> @2640r
		erased:	2720r	%106:vsrc = COPY %288:vsrc
		updated: 2736B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2832B	%111:vsrc = COPY %288:vsrc
	Success: %106 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2832r:16)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r weight:0.000000e+00
2768B	%109:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %109 in %290
		RHS = %109 [2768r,2784r:0)[2784r,2864r:1)  0 at 2768r 1 at 2784r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2768r:16)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r weight:0.000000e+00
		merge %109:0 at 2768r into %290:16 at 2672r --> @2672r
		erased:	2768r	%109:vsrc = COPY %290:vsrc
		updated: 2784B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2864B	%112:vsrc = COPY %290:vsrc
	Success: %109 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2864r:17)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r weight:0.000000e+00
2800B	%110:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %110 in %289
		RHS = %110 [2800r,2816r:0)[2816r,2896r:1)  0 at 2800r 1 at 2816r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2800r:16)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r weight:0.000000e+00
		merge %110:0 at 2800r into %289:16 at 2704r --> @2704r
		erased:	2800r	%110:vsrc = COPY %289:vsrc
		updated: 2816B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2896B	%113:vsrc = COPY %289:vsrc
	Success: %110 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2896r:17)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r weight:0.000000e+00
2832B	%111:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %111 in %288
		RHS = %111 [2832r,2848r:0)[2848r,2928r:1)  0 at 2832r 1 at 2848r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2832r:16)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r weight:0.000000e+00
		merge %111:0 at 2832r into %288:16 at 2736r --> @2736r
		erased:	2832r	%111:vsrc = COPY %288:vsrc
		updated: 2848B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %108:vsrc, %50:vsrc, implicit $rm
		updated: 2928B	%114:vsrc = COPY %288:vsrc
	Success: %111 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2928r:17)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r weight:0.000000e+00
2864B	%112:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %112 in %290
		RHS = %112 [2864r,2880r:0)[2880r,2976r:1)  0 at 2864r 1 at 2880r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2864r:17)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r weight:0.000000e+00
		merge %112:0 at 2864r into %290:17 at 2784r --> @2784r
		erased:	2864r	%112:vsrc = COPY %290:vsrc
		updated: 2880B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 2976B	%117:vsrc = COPY %290:vsrc
	Success: %112 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2976r:18)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r weight:0.000000e+00
2896B	%113:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %113 in %289
		RHS = %113 [2896r,2912r:0)[2912r,3008r:1)  0 at 2896r 1 at 2912r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2896r:17)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r weight:0.000000e+00
		merge %113:0 at 2896r into %289:17 at 2816r --> @2816r
		erased:	2896r	%113:vsrc = COPY %289:vsrc
		updated: 2912B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %108:vsrc, %50:vsrc, implicit $rm
		updated: 3008B	%118:vsrc = COPY %289:vsrc
	Success: %113 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3008r:18)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r weight:0.000000e+00
2928B	%114:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %114 in %288
		RHS = %114 [2928r,2944r:0)[2944r,3040r:1)  0 at 2928r 1 at 2944r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2928r:17)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r weight:0.000000e+00
		merge %114:0 at 2928r into %288:17 at 2848r --> @2848r
		erased:	2928r	%114:vsrc = COPY %288:vsrc
		updated: 2944B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 3040B	%119:vsrc = COPY %288:vsrc
	Success: %114 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3040r:18)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r weight:0.000000e+00
2976B	%117:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %117 in %290
		RHS = %117 [2976r,2992r:0)[2992r,3072r:1)  0 at 2976r 1 at 2992r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2976r:18)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r weight:0.000000e+00
		merge %117:0 at 2976r into %290:18 at 2880r --> @2880r
		erased:	2976r	%117:vsrc = COPY %290:vsrc
		updated: 2992B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 3072B	%120:vsrc = COPY %290:vsrc
	Success: %117 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3072r:19)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r weight:0.000000e+00
3008B	%118:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %118 in %289
		RHS = %118 [3008r,3024r:0)[3024r,3104r:1)  0 at 3008r 1 at 3024r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3008r:18)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r weight:0.000000e+00
		merge %118:0 at 3008r into %289:18 at 2912r --> @2912r
		erased:	3008r	%118:vsrc = COPY %289:vsrc
		updated: 3024B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 3104B	%121:vsrc = COPY %289:vsrc
	Success: %118 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3104r:19)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r weight:0.000000e+00
3040B	%119:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %119 in %288
		RHS = %119 [3040r,3056r:0)[3056r,3136r:1)  0 at 3040r 1 at 3056r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3040r:18)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r weight:0.000000e+00
		merge %119:0 at 3040r into %288:18 at 2944r --> @2944r
		erased:	3040r	%119:vsrc = COPY %288:vsrc
		updated: 3056B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 3136B	%122:vsrc = COPY %288:vsrc
	Success: %119 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3136r:19)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r weight:0.000000e+00
3072B	%120:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %120 in %290
		RHS = %120 [3072r,3088r:0)[3088r,3280r:1)  0 at 3072r 1 at 3088r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3072r:19)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r weight:0.000000e+00
		merge %120:0 at 3072r into %290:19 at 2992r --> @2992r
		erased:	3072r	%120:vsrc = COPY %290:vsrc
		updated: 3088B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 3280B	%133:vsrc = COPY %290:vsrc
	Success: %120 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3280r:20)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r weight:0.000000e+00
3104B	%121:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %121 in %289
		RHS = %121 [3104r,3120r:0)[3120r,3312r:1)  0 at 3104r 1 at 3120r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3104r:19)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r weight:0.000000e+00
		merge %121:0 at 3104r into %289:19 at 3024r --> @3024r
		erased:	3104r	%121:vsrc = COPY %289:vsrc
		updated: 3120B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 3312B	%135:vsrc = COPY %289:vsrc
	Success: %121 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3312r:20)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r weight:0.000000e+00
3136B	%122:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %122 in %288
		RHS = %122 [3136r,3152r:0)[3152r,3344r:1)  0 at 3136r 1 at 3152r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3136r:19)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r weight:0.000000e+00
		merge %122:0 at 3136r into %288:19 at 3056r --> @3056r
		erased:	3136r	%122:vsrc = COPY %288:vsrc
		updated: 3152B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %50:vsrc, %50:vsrc, implicit $rm
		updated: 3344B	%136:vsrc = COPY %288:vsrc
	Success: %122 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3344r:20)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r weight:0.000000e+00
3216B	%128:vsrc = COPY %125.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %128 in %125:sub_vsx0
		RHS = %128 [3216r,3424r:0)  0 at 3216r weight:0.000000e+00
		LHS = %125 [3184r,3232r:0)  0 at 3184r L0000000000000002 [3184r,3216r:0)  0 at 3184r L0000000000000040 [3184r,3232r:0)  0 at 3184r weight:0.000000e+00
		merge %128:0 at 3216r into %125:0 at 3184r --> @3184r
		LHST = %125 %125 [3184r,3232r:0)  0 at 3184r L0000000000000002 [3184r,3216r:0)  0 at 3184r L0000000000000040 [3184r,3232r:0)  0 at 3184r weight:0.000000e+00
		merge %128:0 at 3216r into %125:0 at 3184r --> @3184r
		joined lanes: 0000000000000002 [3184r,3424r:0)  0 at 3184r
	Joined SubRanges %125 [3184r,3232r:0)  0 at 3184r L0000000000000002 [3184r,3424r:0)  0 at 3184r L0000000000000040 [3184r,3232r:0)  0 at 3184r weight:0.000000e+00
		Expecting instruction removal at 3216r
		erased:	3216r	%128:vsrc = COPY %125.sub_vsx0:vsrprc
		updated: 3392B	%138:vsrc = contract nofpexcept XVMADDADP %138:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %50:vsrc, implicit $rm
		updated: 3424B	%140:vsrc = contract nofpexcept XVMADDADP %140:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %5:vsrc, implicit $rm
	Success: %128:sub_vsx0 -> %125
	Result = %125 [3184r,3424r:0)  0 at 3184r L0000000000000002 [3184r,3424r:0)  0 at 3184r L0000000000000040 [3184r,3232r:0)  0 at 3184r weight:0.000000e+00
3232B	%129:vsrc = COPY %125.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %129 in %125:sub_vsx1
		RHS = %129 [3232r,3328r:0)  0 at 3232r weight:0.000000e+00
		LHS = %125 [3184r,3424r:0)  0 at 3184r L0000000000000002 [3184r,3424r:0)  0 at 3184r L0000000000000040 [3184r,3232r:0)  0 at 3184r weight:0.000000e+00
		merge %129:0 at 3232r into %125:0 at 3184r --> @3184r
		LHST = %125 %125 [3184r,3424r:0)  0 at 3184r L0000000000000002 [3184r,3424r:0)  0 at 3184r L0000000000000040 [3184r,3232r:0)  0 at 3184r weight:0.000000e+00
		merge %129:0 at 3232r into %125:0 at 3184r --> @3184r
		joined lanes: 0000000000000040 [3184r,3328r:0)  0 at 3184r
	Joined SubRanges %125 [3184r,3424r:0)  0 at 3184r L0000000000000002 [3184r,3424r:0)  0 at 3184r L0000000000000040 [3184r,3328r:0)  0 at 3184r weight:0.000000e+00
		Expecting instruction removal at 3232r
		erased:	3232r	%129:vsrc = COPY %125.sub_vsx1:vsrprc
		updated: 3296B	%133:vsrc = contract nofpexcept XVMADDADP %133:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %116:vsrc, implicit $rm
		updated: 3328B	%135:vsrc = contract nofpexcept XVMADDADP %135:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %50:vsrc, implicit $rm
	Success: %129:sub_vsx1 -> %125
	Result = %125 [3184r,3424r:0)  0 at 3184r L0000000000000002 [3184r,3424r:0)  0 at 3184r L0000000000000040 [3184r,3328r:0)  0 at 3184r weight:0.000000e+00
3248B	%130:vsrc = COPY %127.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %130 in %127:sub_vsx0
		RHS = %130 [3248r,3456r:0)  0 at 3248r weight:0.000000e+00
		LHS = %127 [3200r,3264r:0)  0 at 3200r L0000000000000002 [3200r,3248r:0)  0 at 3200r L0000000000000040 [3200r,3264r:0)  0 at 3200r weight:0.000000e+00
		merge %130:0 at 3248r into %127:0 at 3200r --> @3200r
		LHST = %127 %127 [3200r,3264r:0)  0 at 3200r L0000000000000002 [3200r,3248r:0)  0 at 3200r L0000000000000040 [3200r,3264r:0)  0 at 3200r weight:0.000000e+00
		merge %130:0 at 3248r into %127:0 at 3200r --> @3200r
		joined lanes: 0000000000000002 [3200r,3456r:0)  0 at 3200r
	Joined SubRanges %127 [3200r,3264r:0)  0 at 3200r L0000000000000002 [3200r,3456r:0)  0 at 3200r L0000000000000040 [3200r,3264r:0)  0 at 3200r weight:0.000000e+00
		Expecting instruction removal at 3248r
		erased:	3248r	%130:vsrc = COPY %127.sub_vsx0:vsrprc
		updated: 3456B	%141:vsrc = contract nofpexcept XVMADDADP %141:vsrc(tied-def 0), %127.sub_vsx0:vsrprc, %124:vsrc, implicit $rm
	Success: %130:sub_vsx0 -> %127
	Result = %127 [3200r,3456r:0)  0 at 3200r L0000000000000002 [3200r,3456r:0)  0 at 3200r L0000000000000040 [3200r,3264r:0)  0 at 3200r weight:0.000000e+00
3264B	%131:vsrc = COPY %127.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %131 in %127:sub_vsx1
		RHS = %131 [3264r,3360r:0)  0 at 3264r weight:0.000000e+00
		LHS = %127 [3200r,3456r:0)  0 at 3200r L0000000000000002 [3200r,3456r:0)  0 at 3200r L0000000000000040 [3200r,3264r:0)  0 at 3200r weight:0.000000e+00
		merge %131:0 at 3264r into %127:0 at 3200r --> @3200r
		LHST = %127 %127 [3200r,3456r:0)  0 at 3200r L0000000000000002 [3200r,3456r:0)  0 at 3200r L0000000000000040 [3200r,3264r:0)  0 at 3200r weight:0.000000e+00
		merge %131:0 at 3264r into %127:0 at 3200r --> @3200r
		joined lanes: 0000000000000040 [3200r,3360r:0)  0 at 3200r
	Joined SubRanges %127 [3200r,3456r:0)  0 at 3200r L0000000000000002 [3200r,3456r:0)  0 at 3200r L0000000000000040 [3200r,3360r:0)  0 at 3200r weight:0.000000e+00
		Expecting instruction removal at 3264r
		erased:	3264r	%131:vsrc = COPY %127.sub_vsx1:vsrprc
		updated: 3360B	%136:vsrc = contract nofpexcept XVMADDADP %136:vsrc(tied-def 0), %127.sub_vsx1:vsrprc, %5:vsrc, implicit $rm
	Success: %131:sub_vsx1 -> %127
	Result = %127 [3200r,3456r:0)  0 at 3200r L0000000000000002 [3200r,3456r:0)  0 at 3200r L0000000000000040 [3200r,3360r:0)  0 at 3200r weight:0.000000e+00
3280B	%133:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %133 in %290
		RHS = %133 [3280r,3296r:0)[3296r,3376r:1)  0 at 3280r 1 at 3296r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3280r:20)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r weight:0.000000e+00
		merge %133:0 at 3280r into %290:20 at 3088r --> @3088r
		erased:	3280r	%133:vsrc = COPY %290:vsrc
		updated: 3296B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %116:vsrc, implicit $rm
		updated: 3376B	%138:vsrc = COPY %290:vsrc
	Success: %133 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3376r:21)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r weight:0.000000e+00
3312B	%135:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %135 in %289
		RHS = %135 [3312r,3328r:0)[3328r,3408r:1)  0 at 3312r 1 at 3328r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3312r:20)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r weight:0.000000e+00
		merge %135:0 at 3312r into %289:20 at 3120r --> @3120r
		erased:	3312r	%135:vsrc = COPY %289:vsrc
		updated: 3328B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %50:vsrc, implicit $rm
		updated: 3408B	%140:vsrc = COPY %289:vsrc
	Success: %135 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3408r:21)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r weight:0.000000e+00
3344B	%136:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %136 in %288
		RHS = %136 [3344r,3360r:0)[3360r,3440r:1)  0 at 3344r 1 at 3360r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3344r:20)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r weight:0.000000e+00
		merge %136:0 at 3344r into %288:20 at 3152r --> @3152r
		erased:	3344r	%136:vsrc = COPY %288:vsrc
		updated: 3360B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %127.sub_vsx1:vsrprc, %5:vsrc, implicit $rm
		updated: 3440B	%141:vsrc = COPY %288:vsrc
	Success: %136 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3440r:21)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r weight:0.000000e+00
3376B	%138:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %138 in %290
		RHS = %138 [3376r,3392r:0)[3392r,3632r:1)  0 at 3376r 1 at 3392r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3376r:21)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r weight:0.000000e+00
		merge %138:0 at 3376r into %290:21 at 3296r --> @3296r
		erased:	3376r	%138:vsrc = COPY %290:vsrc
		updated: 3392B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %50:vsrc, implicit $rm
		updated: 3632B	%158:vsrc = COPY %290:vsrc
	Success: %138 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3632r:22)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r weight:0.000000e+00
3408B	%140:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %140 in %289
		RHS = %140 [3408r,3424r:0)[3424r,3664r:1)  0 at 3408r 1 at 3424r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3408r:21)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r weight:0.000000e+00
		merge %140:0 at 3408r into %289:21 at 3328r --> @3328r
		erased:	3408r	%140:vsrc = COPY %289:vsrc
		updated: 3424B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %5:vsrc, implicit $rm
		updated: 3664B	%160:vsrc = COPY %289:vsrc
	Success: %140 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3664r:22)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r weight:0.000000e+00
3440B	%141:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %141 in %288
		RHS = %141 [3440r,3456r:0)[3456r,3696r:1)  0 at 3440r 1 at 3456r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3440r:21)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r weight:0.000000e+00
		merge %141:0 at 3440r into %288:21 at 3360r --> @3360r
		erased:	3440r	%141:vsrc = COPY %288:vsrc
		updated: 3456B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %127.sub_vsx0:vsrprc, %124:vsrc, implicit $rm
		updated: 3696B	%161:vsrc = COPY %288:vsrc
	Success: %141 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3696r:22)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r weight:0.000000e+00
3568B	%153:vsrc = COPY %150.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %153 in %150:sub_vsx0
		RHS = %153 [3568r,3776r:0)  0 at 3568r weight:0.000000e+00
		LHS = %150 [3536r,3584r:0)  0 at 3536r L0000000000000002 [3536r,3568r:0)  0 at 3536r L0000000000000040 [3536r,3584r:0)  0 at 3536r weight:0.000000e+00
		merge %153:0 at 3568r into %150:0 at 3536r --> @3536r
		LHST = %150 %150 [3536r,3584r:0)  0 at 3536r L0000000000000002 [3536r,3568r:0)  0 at 3536r L0000000000000040 [3536r,3584r:0)  0 at 3536r weight:0.000000e+00
		merge %153:0 at 3568r into %150:0 at 3536r --> @3536r
		joined lanes: 0000000000000002 [3536r,3776r:0)  0 at 3536r
	Joined SubRanges %150 [3536r,3584r:0)  0 at 3536r L0000000000000002 [3536r,3776r:0)  0 at 3536r L0000000000000040 [3536r,3584r:0)  0 at 3536r weight:0.000000e+00
		Expecting instruction removal at 3568r
		erased:	3568r	%153:vsrc = COPY %150.sub_vsx0:vsrprc
		updated: 3744B	%163:vsrc = contract nofpexcept XVMADDADP %163:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %143:vsrc, implicit $rm
		updated: 3776B	%165:vsrc = contract nofpexcept XVMADDADP %165:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %145:vsrc, implicit $rm
	Success: %153:sub_vsx0 -> %150
	Result = %150 [3536r,3776r:0)  0 at 3536r L0000000000000002 [3536r,3776r:0)  0 at 3536r L0000000000000040 [3536r,3584r:0)  0 at 3536r weight:0.000000e+00
3584B	%154:vsrc = COPY %150.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %154 in %150:sub_vsx1
		RHS = %154 [3584r,3680r:0)  0 at 3584r weight:0.000000e+00
		LHS = %150 [3536r,3776r:0)  0 at 3536r L0000000000000002 [3536r,3776r:0)  0 at 3536r L0000000000000040 [3536r,3584r:0)  0 at 3536r weight:0.000000e+00
		merge %154:0 at 3584r into %150:0 at 3536r --> @3536r
		LHST = %150 %150 [3536r,3776r:0)  0 at 3536r L0000000000000002 [3536r,3776r:0)  0 at 3536r L0000000000000040 [3536r,3584r:0)  0 at 3536r weight:0.000000e+00
		merge %154:0 at 3584r into %150:0 at 3536r --> @3536r
		joined lanes: 0000000000000040 [3536r,3680r:0)  0 at 3536r
	Joined SubRanges %150 [3536r,3776r:0)  0 at 3536r L0000000000000002 [3536r,3776r:0)  0 at 3536r L0000000000000040 [3536r,3680r:0)  0 at 3536r weight:0.000000e+00
		Expecting instruction removal at 3584r
		erased:	3584r	%154:vsrc = COPY %150.sub_vsx1:vsrprc
		updated: 3648B	%158:vsrc = contract nofpexcept XVMADDADP %158:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %50:vsrc, implicit $rm
		updated: 3680B	%160:vsrc = contract nofpexcept XVMADDADP %160:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %124:vsrc, implicit $rm
	Success: %154:sub_vsx1 -> %150
	Result = %150 [3536r,3776r:0)  0 at 3536r L0000000000000002 [3536r,3776r:0)  0 at 3536r L0000000000000040 [3536r,3680r:0)  0 at 3536r weight:0.000000e+00
3600B	%155:vsrc = COPY %152.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %155 in %152:sub_vsx0
		RHS = %155 [3600r,3808r:0)  0 at 3600r weight:0.000000e+00
		LHS = %152 [3552r,3616r:0)  0 at 3552r L0000000000000002 [3552r,3600r:0)  0 at 3552r L0000000000000040 [3552r,3616r:0)  0 at 3552r weight:0.000000e+00
		merge %155:0 at 3600r into %152:0 at 3552r --> @3552r
		LHST = %152 %152 [3552r,3616r:0)  0 at 3552r L0000000000000002 [3552r,3600r:0)  0 at 3552r L0000000000000040 [3552r,3616r:0)  0 at 3552r weight:0.000000e+00
		merge %155:0 at 3600r into %152:0 at 3552r --> @3552r
		joined lanes: 0000000000000002 [3552r,3808r:0)  0 at 3552r
	Joined SubRanges %152 [3552r,3616r:0)  0 at 3552r L0000000000000002 [3552r,3808r:0)  0 at 3552r L0000000000000040 [3552r,3616r:0)  0 at 3552r weight:0.000000e+00
		Expecting instruction removal at 3600r
		erased:	3600r	%155:vsrc = COPY %152.sub_vsx0:vsrprc
		updated: 3808B	%166:vsrc = contract nofpexcept XVMADDADP %166:vsrc(tied-def 0), %152.sub_vsx0:vsrprc, %149:vsrc, implicit $rm
	Success: %155:sub_vsx0 -> %152
	Result = %152 [3552r,3808r:0)  0 at 3552r L0000000000000002 [3552r,3808r:0)  0 at 3552r L0000000000000040 [3552r,3616r:0)  0 at 3552r weight:0.000000e+00
3616B	%156:vsrc = COPY %152.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %156 in %152:sub_vsx1
		RHS = %156 [3616r,3712r:0)  0 at 3616r weight:0.000000e+00
		LHS = %152 [3552r,3808r:0)  0 at 3552r L0000000000000002 [3552r,3808r:0)  0 at 3552r L0000000000000040 [3552r,3616r:0)  0 at 3552r weight:0.000000e+00
		merge %156:0 at 3616r into %152:0 at 3552r --> @3552r
		LHST = %152 %152 [3552r,3808r:0)  0 at 3552r L0000000000000002 [3552r,3808r:0)  0 at 3552r L0000000000000040 [3552r,3616r:0)  0 at 3552r weight:0.000000e+00
		merge %156:0 at 3616r into %152:0 at 3552r --> @3552r
		joined lanes: 0000000000000040 [3552r,3712r:0)  0 at 3552r
	Joined SubRanges %152 [3552r,3808r:0)  0 at 3552r L0000000000000002 [3552r,3808r:0)  0 at 3552r L0000000000000040 [3552r,3712r:0)  0 at 3552r weight:0.000000e+00
		Expecting instruction removal at 3616r
		erased:	3616r	%156:vsrc = COPY %152.sub_vsx1:vsrprc
		updated: 3712B	%161:vsrc = contract nofpexcept XVMADDADP %161:vsrc(tied-def 0), %152.sub_vsx1:vsrprc, %145:vsrc, implicit $rm
	Success: %156:sub_vsx1 -> %152
	Result = %152 [3552r,3808r:0)  0 at 3552r L0000000000000002 [3552r,3808r:0)  0 at 3552r L0000000000000040 [3552r,3712r:0)  0 at 3552r weight:0.000000e+00
3632B	%158:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %158 in %290
		RHS = %158 [3632r,3648r:0)[3648r,3728r:1)  0 at 3632r 1 at 3648r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3632r:22)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r weight:0.000000e+00
		merge %158:0 at 3632r into %290:22 at 3392r --> @3392r
		erased:	3632r	%158:vsrc = COPY %290:vsrc
		updated: 3648B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %50:vsrc, implicit $rm
		updated: 3728B	%163:vsrc = COPY %290:vsrc
	Success: %158 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3728r:23)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r weight:0.000000e+00
3664B	%160:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %160 in %289
		RHS = %160 [3664r,3680r:0)[3680r,3760r:1)  0 at 3664r 1 at 3680r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3664r:22)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r weight:0.000000e+00
		merge %160:0 at 3664r into %289:22 at 3424r --> @3424r
		erased:	3664r	%160:vsrc = COPY %289:vsrc
		updated: 3680B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %124:vsrc, implicit $rm
		updated: 3760B	%165:vsrc = COPY %289:vsrc
	Success: %160 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3760r:23)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r weight:0.000000e+00
3696B	%161:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %161 in %288
		RHS = %161 [3696r,3712r:0)[3712r,3792r:1)  0 at 3696r 1 at 3712r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3696r:22)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r weight:0.000000e+00
		merge %161:0 at 3696r into %288:22 at 3456r --> @3456r
		erased:	3696r	%161:vsrc = COPY %288:vsrc
		updated: 3712B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %152.sub_vsx1:vsrprc, %145:vsrc, implicit $rm
		updated: 3792B	%166:vsrc = COPY %288:vsrc
	Success: %161 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3792r:23)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r weight:0.000000e+00
3728B	%163:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %163 in %290
		RHS = %163 [3728r,3744r:0)[3744r,3984r:1)  0 at 3728r 1 at 3744r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3728r:23)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r weight:0.000000e+00
		merge %163:0 at 3728r into %290:23 at 3648r --> @3648r
		erased:	3728r	%163:vsrc = COPY %290:vsrc
		updated: 3744B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %143:vsrc, implicit $rm
		updated: 3984B	%183:vsrc = COPY %290:vsrc
	Success: %163 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,3984r:24)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r weight:0.000000e+00
3760B	%165:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %165 in %289
		RHS = %165 [3760r,3776r:0)[3776r,4016r:1)  0 at 3760r 1 at 3776r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3760r:23)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r weight:0.000000e+00
		merge %165:0 at 3760r into %289:23 at 3680r --> @3680r
		erased:	3760r	%165:vsrc = COPY %289:vsrc
		updated: 3776B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %145:vsrc, implicit $rm
		updated: 4016B	%185:vsrc = COPY %289:vsrc
	Success: %165 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4016r:24)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r weight:0.000000e+00
3792B	%166:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %166 in %288
		RHS = %166 [3792r,3808r:0)[3808r,4048r:1)  0 at 3792r 1 at 3808r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3792r:23)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r weight:0.000000e+00
		merge %166:0 at 3792r into %288:23 at 3712r --> @3712r
		erased:	3792r	%166:vsrc = COPY %288:vsrc
		updated: 3808B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %152.sub_vsx0:vsrprc, %149:vsrc, implicit $rm
		updated: 4048B	%186:vsrc = COPY %288:vsrc
	Success: %166 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4048r:24)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r weight:0.000000e+00
3920B	%178:vsrc = COPY %175.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %178 in %175:sub_vsx0
		RHS = %178 [3920r,4128r:0)  0 at 3920r weight:0.000000e+00
		LHS = %175 [3888r,3936r:0)  0 at 3888r L0000000000000002 [3888r,3920r:0)  0 at 3888r L0000000000000040 [3888r,3936r:0)  0 at 3888r weight:0.000000e+00
		merge %178:0 at 3920r into %175:0 at 3888r --> @3888r
		LHST = %175 %175 [3888r,3936r:0)  0 at 3888r L0000000000000002 [3888r,3920r:0)  0 at 3888r L0000000000000040 [3888r,3936r:0)  0 at 3888r weight:0.000000e+00
		merge %178:0 at 3920r into %175:0 at 3888r --> @3888r
		joined lanes: 0000000000000002 [3888r,4128r:0)  0 at 3888r
	Joined SubRanges %175 [3888r,3936r:0)  0 at 3888r L0000000000000002 [3888r,4128r:0)  0 at 3888r L0000000000000040 [3888r,3936r:0)  0 at 3888r weight:0.000000e+00
		Expecting instruction removal at 3920r
		erased:	3920r	%178:vsrc = COPY %175.sub_vsx0:vsrprc
		updated: 4096B	%188:vsrc = contract nofpexcept XVMADDADP %188:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %168:vsrc, implicit $rm
		updated: 4128B	%190:vsrc = contract nofpexcept XVMADDADP %190:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %170:vsrc, implicit $rm
	Success: %178:sub_vsx0 -> %175
	Result = %175 [3888r,4128r:0)  0 at 3888r L0000000000000002 [3888r,4128r:0)  0 at 3888r L0000000000000040 [3888r,3936r:0)  0 at 3888r weight:0.000000e+00
3936B	%179:vsrc = COPY %175.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %179 in %175:sub_vsx1
		RHS = %179 [3936r,4032r:0)  0 at 3936r weight:0.000000e+00
		LHS = %175 [3888r,4128r:0)  0 at 3888r L0000000000000002 [3888r,4128r:0)  0 at 3888r L0000000000000040 [3888r,3936r:0)  0 at 3888r weight:0.000000e+00
		merge %179:0 at 3936r into %175:0 at 3888r --> @3888r
		LHST = %175 %175 [3888r,4128r:0)  0 at 3888r L0000000000000002 [3888r,4128r:0)  0 at 3888r L0000000000000040 [3888r,3936r:0)  0 at 3888r weight:0.000000e+00
		merge %179:0 at 3936r into %175:0 at 3888r --> @3888r
		joined lanes: 0000000000000040 [3888r,4032r:0)  0 at 3888r
	Joined SubRanges %175 [3888r,4128r:0)  0 at 3888r L0000000000000002 [3888r,4128r:0)  0 at 3888r L0000000000000040 [3888r,4032r:0)  0 at 3888r weight:0.000000e+00
		Expecting instruction removal at 3936r
		erased:	3936r	%179:vsrc = COPY %175.sub_vsx1:vsrprc
		updated: 4000B	%183:vsrc = contract nofpexcept XVMADDADP %183:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %147:vsrc, implicit $rm
		updated: 4032B	%185:vsrc = contract nofpexcept XVMADDADP %185:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %149:vsrc, implicit $rm
	Success: %179:sub_vsx1 -> %175
	Result = %175 [3888r,4128r:0)  0 at 3888r L0000000000000002 [3888r,4128r:0)  0 at 3888r L0000000000000040 [3888r,4032r:0)  0 at 3888r weight:0.000000e+00
3952B	%180:vsrc = COPY %177.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %180 in %177:sub_vsx0
		RHS = %180 [3952r,4160r:0)  0 at 3952r weight:0.000000e+00
		LHS = %177 [3904r,3968r:0)  0 at 3904r L0000000000000002 [3904r,3952r:0)  0 at 3904r L0000000000000040 [3904r,3968r:0)  0 at 3904r weight:0.000000e+00
		merge %180:0 at 3952r into %177:0 at 3904r --> @3904r
		LHST = %177 %177 [3904r,3968r:0)  0 at 3904r L0000000000000002 [3904r,3952r:0)  0 at 3904r L0000000000000040 [3904r,3968r:0)  0 at 3904r weight:0.000000e+00
		merge %180:0 at 3952r into %177:0 at 3904r --> @3904r
		joined lanes: 0000000000000002 [3904r,4160r:0)  0 at 3904r
	Joined SubRanges %177 [3904r,3968r:0)  0 at 3904r L0000000000000002 [3904r,4160r:0)  0 at 3904r L0000000000000040 [3904r,3968r:0)  0 at 3904r weight:0.000000e+00
		Expecting instruction removal at 3952r
		erased:	3952r	%180:vsrc = COPY %177.sub_vsx0:vsrprc
		updated: 4160B	%191:vsrc = contract nofpexcept XVMADDADP %191:vsrc(tied-def 0), %177.sub_vsx0:vsrprc, %174:vsrc, implicit $rm
	Success: %180:sub_vsx0 -> %177
	Result = %177 [3904r,4160r:0)  0 at 3904r L0000000000000002 [3904r,4160r:0)  0 at 3904r L0000000000000040 [3904r,3968r:0)  0 at 3904r weight:0.000000e+00
3968B	%181:vsrc = COPY %177.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %181 in %177:sub_vsx1
		RHS = %181 [3968r,4064r:0)  0 at 3968r weight:0.000000e+00
		LHS = %177 [3904r,4160r:0)  0 at 3904r L0000000000000002 [3904r,4160r:0)  0 at 3904r L0000000000000040 [3904r,3968r:0)  0 at 3904r weight:0.000000e+00
		merge %181:0 at 3968r into %177:0 at 3904r --> @3904r
		LHST = %177 %177 [3904r,4160r:0)  0 at 3904r L0000000000000002 [3904r,4160r:0)  0 at 3904r L0000000000000040 [3904r,3968r:0)  0 at 3904r weight:0.000000e+00
		merge %181:0 at 3968r into %177:0 at 3904r --> @3904r
		joined lanes: 0000000000000040 [3904r,4064r:0)  0 at 3904r
	Joined SubRanges %177 [3904r,4160r:0)  0 at 3904r L0000000000000002 [3904r,4160r:0)  0 at 3904r L0000000000000040 [3904r,4064r:0)  0 at 3904r weight:0.000000e+00
		Expecting instruction removal at 3968r
		erased:	3968r	%181:vsrc = COPY %177.sub_vsx1:vsrprc
		updated: 4064B	%186:vsrc = contract nofpexcept XVMADDADP %186:vsrc(tied-def 0), %177.sub_vsx1:vsrprc, %170:vsrc, implicit $rm
	Success: %181:sub_vsx1 -> %177
	Result = %177 [3904r,4160r:0)  0 at 3904r L0000000000000002 [3904r,4160r:0)  0 at 3904r L0000000000000040 [3904r,4064r:0)  0 at 3904r weight:0.000000e+00
3984B	%183:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %183 in %290
		RHS = %183 [3984r,4000r:0)[4000r,4080r:1)  0 at 3984r 1 at 4000r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,3984r:24)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r weight:0.000000e+00
		merge %183:0 at 3984r into %290:24 at 3744r --> @3744r
		erased:	3984r	%183:vsrc = COPY %290:vsrc
		updated: 4000B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %147:vsrc, implicit $rm
		updated: 4080B	%188:vsrc = COPY %290:vsrc
	Success: %183 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4080r:25)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r weight:0.000000e+00
4016B	%185:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %185 in %289
		RHS = %185 [4016r,4032r:0)[4032r,4112r:1)  0 at 4016r 1 at 4032r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4016r:24)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r weight:0.000000e+00
		merge %185:0 at 4016r into %289:24 at 3776r --> @3776r
		erased:	4016r	%185:vsrc = COPY %289:vsrc
		updated: 4032B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %149:vsrc, implicit $rm
		updated: 4112B	%190:vsrc = COPY %289:vsrc
	Success: %185 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4112r:25)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r weight:0.000000e+00
4048B	%186:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %186 in %288
		RHS = %186 [4048r,4064r:0)[4064r,4144r:1)  0 at 4048r 1 at 4064r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4048r:24)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r weight:0.000000e+00
		merge %186:0 at 4048r into %288:24 at 3808r --> @3808r
		erased:	4048r	%186:vsrc = COPY %288:vsrc
		updated: 4064B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %177.sub_vsx1:vsrprc, %170:vsrc, implicit $rm
		updated: 4144B	%191:vsrc = COPY %288:vsrc
	Success: %186 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4144r:25)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r weight:0.000000e+00
4080B	%188:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %188 in %290
		RHS = %188 [4080r,4096r:0)[4096r,4320r:1)  0 at 4080r 1 at 4096r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4080r:25)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r weight:0.000000e+00
		merge %188:0 at 4080r into %290:25 at 4000r --> @4000r
		erased:	4080r	%188:vsrc = COPY %290:vsrc
		updated: 4096B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %168:vsrc, implicit $rm
		updated: 4320B	%206:vsrc = COPY %290:vsrc
	Success: %188 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4320r:26)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r weight:0.000000e+00
4112B	%190:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %190 in %289
		RHS = %190 [4112r,4128r:0)[4128r,4352r:1)  0 at 4112r 1 at 4128r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4112r:25)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r weight:0.000000e+00
		merge %190:0 at 4112r into %289:25 at 4032r --> @4032r
		erased:	4112r	%190:vsrc = COPY %289:vsrc
		updated: 4128B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %170:vsrc, implicit $rm
		updated: 4352B	%208:vsrc = COPY %289:vsrc
	Success: %190 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4352r:26)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r weight:0.000000e+00
4144B	%191:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %191 in %288
		RHS = %191 [4144r,4160r:0)[4160r,4384r:1)  0 at 4144r 1 at 4160r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4144r:25)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r weight:0.000000e+00
		merge %191:0 at 4144r into %288:25 at 4064r --> @4064r
		erased:	4144r	%191:vsrc = COPY %288:vsrc
		updated: 4160B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %177.sub_vsx0:vsrprc, %174:vsrc, implicit $rm
		updated: 4384B	%209:vsrc = COPY %288:vsrc
	Success: %191 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4384r:26)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r weight:0.000000e+00
4256B	%201:vsrc = COPY %198.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %201 in %198:sub_vsx0
		RHS = %201 [4256r,4464r:0)  0 at 4256r weight:0.000000e+00
		LHS = %198 [4224r,4272r:0)  0 at 4224r L0000000000000002 [4224r,4256r:0)  0 at 4224r L0000000000000040 [4224r,4272r:0)  0 at 4224r weight:0.000000e+00
		merge %201:0 at 4256r into %198:0 at 4224r --> @4224r
		LHST = %198 %198 [4224r,4272r:0)  0 at 4224r L0000000000000002 [4224r,4256r:0)  0 at 4224r L0000000000000040 [4224r,4272r:0)  0 at 4224r weight:0.000000e+00
		merge %201:0 at 4256r into %198:0 at 4224r --> @4224r
		joined lanes: 0000000000000002 [4224r,4464r:0)  0 at 4224r
	Joined SubRanges %198 [4224r,4272r:0)  0 at 4224r L0000000000000002 [4224r,4464r:0)  0 at 4224r L0000000000000040 [4224r,4272r:0)  0 at 4224r weight:0.000000e+00
		Expecting instruction removal at 4256r
		erased:	4256r	%201:vsrc = COPY %198.sub_vsx0:vsrprc
		updated: 4432B	%211:vsrc = contract nofpexcept XVMADDADP %211:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %193:vsrc, implicit $rm
		updated: 4464B	%213:vsrc = contract nofpexcept XVMADDADP %213:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %195:vsrc, implicit $rm
	Success: %201:sub_vsx0 -> %198
	Result = %198 [4224r,4464r:0)  0 at 4224r L0000000000000002 [4224r,4464r:0)  0 at 4224r L0000000000000040 [4224r,4272r:0)  0 at 4224r weight:0.000000e+00
4272B	%202:vsrc = COPY %198.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %202 in %198:sub_vsx1
		RHS = %202 [4272r,4368r:0)  0 at 4272r weight:0.000000e+00
		LHS = %198 [4224r,4464r:0)  0 at 4224r L0000000000000002 [4224r,4464r:0)  0 at 4224r L0000000000000040 [4224r,4272r:0)  0 at 4224r weight:0.000000e+00
		merge %202:0 at 4272r into %198:0 at 4224r --> @4224r
		LHST = %198 %198 [4224r,4464r:0)  0 at 4224r L0000000000000002 [4224r,4464r:0)  0 at 4224r L0000000000000040 [4224r,4272r:0)  0 at 4224r weight:0.000000e+00
		merge %202:0 at 4272r into %198:0 at 4224r --> @4224r
		joined lanes: 0000000000000040 [4224r,4368r:0)  0 at 4224r
	Joined SubRanges %198 [4224r,4464r:0)  0 at 4224r L0000000000000002 [4224r,4464r:0)  0 at 4224r L0000000000000040 [4224r,4368r:0)  0 at 4224r weight:0.000000e+00
		Expecting instruction removal at 4272r
		erased:	4272r	%202:vsrc = COPY %198.sub_vsx1:vsrprc
		updated: 4336B	%206:vsrc = contract nofpexcept XVMADDADP %206:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %172:vsrc, implicit $rm
		updated: 4368B	%208:vsrc = contract nofpexcept XVMADDADP %208:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %174:vsrc, implicit $rm
	Success: %202:sub_vsx1 -> %198
	Result = %198 [4224r,4464r:0)  0 at 4224r L0000000000000002 [4224r,4464r:0)  0 at 4224r L0000000000000040 [4224r,4368r:0)  0 at 4224r weight:0.000000e+00
4288B	%203:vsrc = COPY %200.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %203 in %200:sub_vsx0
		RHS = %203 [4288r,4496r:0)  0 at 4288r weight:0.000000e+00
		LHS = %200 [4240r,4304r:0)  0 at 4240r L0000000000000002 [4240r,4288r:0)  0 at 4240r L0000000000000040 [4240r,4304r:0)  0 at 4240r weight:0.000000e+00
		merge %203:0 at 4288r into %200:0 at 4240r --> @4240r
		LHST = %200 %200 [4240r,4304r:0)  0 at 4240r L0000000000000002 [4240r,4288r:0)  0 at 4240r L0000000000000040 [4240r,4304r:0)  0 at 4240r weight:0.000000e+00
		merge %203:0 at 4288r into %200:0 at 4240r --> @4240r
		joined lanes: 0000000000000002 [4240r,4496r:0)  0 at 4240r
	Joined SubRanges %200 [4240r,4304r:0)  0 at 4240r L0000000000000002 [4240r,4496r:0)  0 at 4240r L0000000000000040 [4240r,4304r:0)  0 at 4240r weight:0.000000e+00
		Expecting instruction removal at 4288r
		erased:	4288r	%203:vsrc = COPY %200.sub_vsx0:vsrprc
		updated: 4496B	%214:vsrc = contract nofpexcept XVMADDADP %214:vsrc(tied-def 0), %200.sub_vsx0:vsrprc, %197:vsrc, implicit $rm
	Success: %203:sub_vsx0 -> %200
	Result = %200 [4240r,4496r:0)  0 at 4240r L0000000000000002 [4240r,4496r:0)  0 at 4240r L0000000000000040 [4240r,4304r:0)  0 at 4240r weight:0.000000e+00
4304B	%204:vsrc = COPY %200.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %204 in %200:sub_vsx1
		RHS = %204 [4304r,4400r:0)  0 at 4304r weight:0.000000e+00
		LHS = %200 [4240r,4496r:0)  0 at 4240r L0000000000000002 [4240r,4496r:0)  0 at 4240r L0000000000000040 [4240r,4304r:0)  0 at 4240r weight:0.000000e+00
		merge %204:0 at 4304r into %200:0 at 4240r --> @4240r
		LHST = %200 %200 [4240r,4496r:0)  0 at 4240r L0000000000000002 [4240r,4496r:0)  0 at 4240r L0000000000000040 [4240r,4304r:0)  0 at 4240r weight:0.000000e+00
		merge %204:0 at 4304r into %200:0 at 4240r --> @4240r
		joined lanes: 0000000000000040 [4240r,4400r:0)  0 at 4240r
	Joined SubRanges %200 [4240r,4496r:0)  0 at 4240r L0000000000000002 [4240r,4496r:0)  0 at 4240r L0000000000000040 [4240r,4400r:0)  0 at 4240r weight:0.000000e+00
		Expecting instruction removal at 4304r
		erased:	4304r	%204:vsrc = COPY %200.sub_vsx1:vsrprc
		updated: 4400B	%209:vsrc = contract nofpexcept XVMADDADP %209:vsrc(tied-def 0), %200.sub_vsx1:vsrprc, %195:vsrc, implicit $rm
	Success: %204:sub_vsx1 -> %200
	Result = %200 [4240r,4496r:0)  0 at 4240r L0000000000000002 [4240r,4496r:0)  0 at 4240r L0000000000000040 [4240r,4400r:0)  0 at 4240r weight:0.000000e+00
4320B	%206:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %206 in %290
		RHS = %206 [4320r,4336r:0)[4336r,4416r:1)  0 at 4320r 1 at 4336r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4320r:26)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r weight:0.000000e+00
		merge %206:0 at 4320r into %290:26 at 4096r --> @4096r
		erased:	4320r	%206:vsrc = COPY %290:vsrc
		updated: 4336B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %172:vsrc, implicit $rm
		updated: 4416B	%211:vsrc = COPY %290:vsrc
	Success: %206 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4416r:27)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r weight:0.000000e+00
4352B	%208:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %208 in %289
		RHS = %208 [4352r,4368r:0)[4368r,4448r:1)  0 at 4352r 1 at 4368r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4352r:26)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r weight:0.000000e+00
		merge %208:0 at 4352r into %289:26 at 4128r --> @4128r
		erased:	4352r	%208:vsrc = COPY %289:vsrc
		updated: 4368B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %174:vsrc, implicit $rm
		updated: 4448B	%213:vsrc = COPY %289:vsrc
	Success: %208 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4448r:27)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r weight:0.000000e+00
4384B	%209:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %209 in %288
		RHS = %209 [4384r,4400r:0)[4400r,4480r:1)  0 at 4384r 1 at 4400r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4384r:26)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r weight:0.000000e+00
		merge %209:0 at 4384r into %288:26 at 4160r --> @4160r
		erased:	4384r	%209:vsrc = COPY %288:vsrc
		updated: 4400B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %200.sub_vsx1:vsrprc, %195:vsrc, implicit $rm
		updated: 4480B	%214:vsrc = COPY %288:vsrc
	Success: %209 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4480r:27)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r weight:0.000000e+00
4416B	%211:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %211 in %290
		RHS = %211 [4416r,4432r:0)[4432r,4624r:1)  0 at 4416r 1 at 4432r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4416r:27)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r weight:0.000000e+00
		merge %211:0 at 4416r into %290:27 at 4336r --> @4336r
		erased:	4416r	%211:vsrc = COPY %290:vsrc
		updated: 4432B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %193:vsrc, implicit $rm
		updated: 4624B	%225:vsrc = COPY %290:vsrc
	Success: %211 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4624r:28)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r weight:0.000000e+00
4448B	%213:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %213 in %289
		RHS = %213 [4448r,4464r:0)[4464r,4656r:1)  0 at 4448r 1 at 4464r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4448r:27)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r weight:0.000000e+00
		merge %213:0 at 4448r into %289:27 at 4368r --> @4368r
		erased:	4448r	%213:vsrc = COPY %289:vsrc
		updated: 4464B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %195:vsrc, implicit $rm
		updated: 4656B	%227:vsrc = COPY %289:vsrc
	Success: %213 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4656r:28)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r weight:0.000000e+00
4480B	%214:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %214 in %288
		RHS = %214 [4480r,4496r:0)[4496r,4688r:1)  0 at 4480r 1 at 4496r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4480r:27)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r weight:0.000000e+00
		merge %214:0 at 4480r into %288:27 at 4400r --> @4400r
		erased:	4480r	%214:vsrc = COPY %288:vsrc
		updated: 4496B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %200.sub_vsx0:vsrprc, %197:vsrc, implicit $rm
		updated: 4688B	%228:vsrc = COPY %288:vsrc
	Success: %214 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4688r:28)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r weight:0.000000e+00
4560B	%220:vsrc = COPY %217.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %220 in %217:sub_vsx0
		RHS = %220 [4560r,4768r:0)  0 at 4560r weight:0.000000e+00
		LHS = %217 [4528r,4576r:0)  0 at 4528r L0000000000000002 [4528r,4560r:0)  0 at 4528r L0000000000000040 [4528r,4576r:0)  0 at 4528r weight:0.000000e+00
		merge %220:0 at 4560r into %217:0 at 4528r --> @4528r
		LHST = %217 %217 [4528r,4576r:0)  0 at 4528r L0000000000000002 [4528r,4560r:0)  0 at 4528r L0000000000000040 [4528r,4576r:0)  0 at 4528r weight:0.000000e+00
		merge %220:0 at 4560r into %217:0 at 4528r --> @4528r
		joined lanes: 0000000000000002 [4528r,4768r:0)  0 at 4528r
	Joined SubRanges %217 [4528r,4576r:0)  0 at 4528r L0000000000000002 [4528r,4768r:0)  0 at 4528r L0000000000000040 [4528r,4576r:0)  0 at 4528r weight:0.000000e+00
		Expecting instruction removal at 4560r
		erased:	4560r	%220:vsrc = COPY %217.sub_vsx0:vsrprc
		updated: 4736B	%230:vsrc = contract nofpexcept XVMADDADP %230:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %50:vsrc, implicit $rm
		updated: 4768B	%232:vsrc = contract nofpexcept XVMADDADP %232:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
	Success: %220:sub_vsx0 -> %217
	Result = %217 [4528r,4768r:0)  0 at 4528r L0000000000000002 [4528r,4768r:0)  0 at 4528r L0000000000000040 [4528r,4576r:0)  0 at 4528r weight:0.000000e+00
4576B	%221:vsrc = COPY %217.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %221 in %217:sub_vsx1
		RHS = %221 [4576r,4672r:0)  0 at 4576r weight:0.000000e+00
		LHS = %217 [4528r,4768r:0)  0 at 4528r L0000000000000002 [4528r,4768r:0)  0 at 4528r L0000000000000040 [4528r,4576r:0)  0 at 4528r weight:0.000000e+00
		merge %221:0 at 4576r into %217:0 at 4528r --> @4528r
		LHST = %217 %217 [4528r,4768r:0)  0 at 4528r L0000000000000002 [4528r,4768r:0)  0 at 4528r L0000000000000040 [4528r,4576r:0)  0 at 4528r weight:0.000000e+00
		merge %221:0 at 4576r into %217:0 at 4528r --> @4528r
		joined lanes: 0000000000000040 [4528r,4672r:0)  0 at 4528r
	Joined SubRanges %217 [4528r,4768r:0)  0 at 4528r L0000000000000002 [4528r,4768r:0)  0 at 4528r L0000000000000040 [4528r,4672r:0)  0 at 4528r weight:0.000000e+00
		Expecting instruction removal at 4576r
		erased:	4576r	%221:vsrc = COPY %217.sub_vsx1:vsrprc
		updated: 4640B	%225:vsrc = contract nofpexcept XVMADDADP %225:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %50:vsrc, implicit $rm
		updated: 4672B	%227:vsrc = contract nofpexcept XVMADDADP %227:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %197:vsrc, implicit $rm
	Success: %221:sub_vsx1 -> %217
	Result = %217 [4528r,4768r:0)  0 at 4528r L0000000000000002 [4528r,4768r:0)  0 at 4528r L0000000000000040 [4528r,4672r:0)  0 at 4528r weight:0.000000e+00
4592B	%222:vsrc = COPY %219.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %222 in %219:sub_vsx0
		RHS = %222 [4592r,4800r:0)  0 at 4592r weight:0.000000e+00
		LHS = %219 [4544r,4608r:0)  0 at 4544r L0000000000000002 [4544r,4592r:0)  0 at 4544r L0000000000000040 [4544r,4608r:0)  0 at 4544r weight:0.000000e+00
		merge %222:0 at 4592r into %219:0 at 4544r --> @4544r
		LHST = %219 %219 [4544r,4608r:0)  0 at 4544r L0000000000000002 [4544r,4592r:0)  0 at 4544r L0000000000000040 [4544r,4608r:0)  0 at 4544r weight:0.000000e+00
		merge %222:0 at 4592r into %219:0 at 4544r --> @4544r
		joined lanes: 0000000000000002 [4544r,4800r:0)  0 at 4544r
	Joined SubRanges %219 [4544r,4608r:0)  0 at 4544r L0000000000000002 [4544r,4800r:0)  0 at 4544r L0000000000000040 [4544r,4608r:0)  0 at 4544r weight:0.000000e+00
		Expecting instruction removal at 4592r
		erased:	4592r	%222:vsrc = COPY %219.sub_vsx0:vsrprc
		updated: 4800B	%233:vsrc = contract nofpexcept XVMADDADP %233:vsrc(tied-def 0), %219.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
	Success: %222:sub_vsx0 -> %219
	Result = %219 [4544r,4800r:0)  0 at 4544r L0000000000000002 [4544r,4800r:0)  0 at 4544r L0000000000000040 [4544r,4608r:0)  0 at 4544r weight:0.000000e+00
4608B	%223:vsrc = COPY %219.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %223 in %219:sub_vsx1
		RHS = %223 [4608r,4704r:0)  0 at 4608r weight:0.000000e+00
		LHS = %219 [4544r,4800r:0)  0 at 4544r L0000000000000002 [4544r,4800r:0)  0 at 4544r L0000000000000040 [4544r,4608r:0)  0 at 4544r weight:0.000000e+00
		merge %223:0 at 4608r into %219:0 at 4544r --> @4544r
		LHST = %219 %219 [4544r,4800r:0)  0 at 4544r L0000000000000002 [4544r,4800r:0)  0 at 4544r L0000000000000040 [4544r,4608r:0)  0 at 4544r weight:0.000000e+00
		merge %223:0 at 4608r into %219:0 at 4544r --> @4544r
		joined lanes: 0000000000000040 [4544r,4704r:0)  0 at 4544r
	Joined SubRanges %219 [4544r,4800r:0)  0 at 4544r L0000000000000002 [4544r,4800r:0)  0 at 4544r L0000000000000040 [4544r,4704r:0)  0 at 4544r weight:0.000000e+00
		Expecting instruction removal at 4608r
		erased:	4608r	%223:vsrc = COPY %219.sub_vsx1:vsrprc
		updated: 4704B	%228:vsrc = contract nofpexcept XVMADDADP %228:vsrc(tied-def 0), %219.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
	Success: %223:sub_vsx1 -> %219
	Result = %219 [4544r,4800r:0)  0 at 4544r L0000000000000002 [4544r,4800r:0)  0 at 4544r L0000000000000040 [4544r,4704r:0)  0 at 4544r weight:0.000000e+00
4624B	%225:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %225 in %290
		RHS = %225 [4624r,4640r:0)[4640r,4720r:1)  0 at 4624r 1 at 4640r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4624r:28)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r weight:0.000000e+00
		merge %225:0 at 4624r into %290:28 at 4432r --> @4432r
		erased:	4624r	%225:vsrc = COPY %290:vsrc
		updated: 4640B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %50:vsrc, implicit $rm
		updated: 4720B	%230:vsrc = COPY %290:vsrc
	Success: %225 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4720r:29)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r weight:0.000000e+00
4656B	%227:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %227 in %289
		RHS = %227 [4656r,4672r:0)[4672r,4752r:1)  0 at 4656r 1 at 4672r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4656r:28)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r weight:0.000000e+00
		merge %227:0 at 4656r into %289:28 at 4464r --> @4464r
		erased:	4656r	%227:vsrc = COPY %289:vsrc
		updated: 4672B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %197:vsrc, implicit $rm
		updated: 4752B	%232:vsrc = COPY %289:vsrc
	Success: %227 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4752r:29)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r weight:0.000000e+00
4688B	%228:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %228 in %288
		RHS = %228 [4688r,4704r:0)[4704r,4784r:1)  0 at 4688r 1 at 4704r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4688r:28)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r weight:0.000000e+00
		merge %228:0 at 4688r into %288:28 at 4496r --> @4496r
		erased:	4688r	%228:vsrc = COPY %288:vsrc
		updated: 4704B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %219.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
		updated: 4784B	%233:vsrc = COPY %288:vsrc
	Success: %228 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4784r:29)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r weight:0.000000e+00
4720B	%230:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %230 in %290
		RHS = %230 [4720r,4736r:0)[4736r,4976r:1)  0 at 4720r 1 at 4736r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4720r:29)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r weight:0.000000e+00
		merge %230:0 at 4720r into %290:29 at 4640r --> @4640r
		erased:	4720r	%230:vsrc = COPY %290:vsrc
		updated: 4736B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %50:vsrc, implicit $rm
		updated: 4976B	%250:vsrc = COPY %290:vsrc
	Success: %230 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4976r:30)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r weight:0.000000e+00
4752B	%232:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %232 in %289
		RHS = %232 [4752r,4768r:0)[4768r,5008r:1)  0 at 4752r 1 at 4768r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4752r:29)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r weight:0.000000e+00
		merge %232:0 at 4752r into %289:29 at 4672r --> @4672r
		erased:	4752r	%232:vsrc = COPY %289:vsrc
		updated: 4768B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
		updated: 5008B	%252:vsrc = COPY %289:vsrc
	Success: %232 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5008r:30)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r weight:0.000000e+00
4784B	%233:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %233 in %288
		RHS = %233 [4784r,4800r:0)[4800r,5040r:1)  0 at 4784r 1 at 4800r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4784r:29)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r weight:0.000000e+00
		merge %233:0 at 4784r into %288:29 at 4704r --> @4704r
		erased:	4784r	%233:vsrc = COPY %288:vsrc
		updated: 4800B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %219.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
		updated: 5040B	%253:vsrc = COPY %288:vsrc
	Success: %233 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5040r:30)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r weight:0.000000e+00
4912B	%245:vsrc = COPY %242.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %245 in %242:sub_vsx0
		RHS = %245 [4912r,5120r:0)  0 at 4912r weight:0.000000e+00
		LHS = %242 [4880r,4928r:0)  0 at 4880r L0000000000000002 [4880r,4912r:0)  0 at 4880r L0000000000000040 [4880r,4928r:0)  0 at 4880r weight:0.000000e+00
		merge %245:0 at 4912r into %242:0 at 4880r --> @4880r
		LHST = %242 %242 [4880r,4928r:0)  0 at 4880r L0000000000000002 [4880r,4912r:0)  0 at 4880r L0000000000000040 [4880r,4928r:0)  0 at 4880r weight:0.000000e+00
		merge %245:0 at 4912r into %242:0 at 4880r --> @4880r
		joined lanes: 0000000000000002 [4880r,5120r:0)  0 at 4880r
	Joined SubRanges %242 [4880r,4928r:0)  0 at 4880r L0000000000000002 [4880r,5120r:0)  0 at 4880r L0000000000000040 [4880r,4928r:0)  0 at 4880r weight:0.000000e+00
		Expecting instruction removal at 4912r
		erased:	4912r	%245:vsrc = COPY %242.sub_vsx0:vsrprc
		updated: 5088B	%255:vsrc = contract nofpexcept XVMADDADP %255:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %235:vsrc, implicit $rm
		updated: 5120B	%257:vsrc = contract nofpexcept XVMADDADP %257:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %237:vsrc, implicit $rm
	Success: %245:sub_vsx0 -> %242
	Result = %242 [4880r,5120r:0)  0 at 4880r L0000000000000002 [4880r,5120r:0)  0 at 4880r L0000000000000040 [4880r,4928r:0)  0 at 4880r weight:0.000000e+00
4928B	%246:vsrc = COPY %242.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %246 in %242:sub_vsx1
		RHS = %246 [4928r,5024r:0)  0 at 4928r weight:0.000000e+00
		LHS = %242 [4880r,5120r:0)  0 at 4880r L0000000000000002 [4880r,5120r:0)  0 at 4880r L0000000000000040 [4880r,4928r:0)  0 at 4880r weight:0.000000e+00
		merge %246:0 at 4928r into %242:0 at 4880r --> @4880r
		LHST = %242 %242 [4880r,5120r:0)  0 at 4880r L0000000000000002 [4880r,5120r:0)  0 at 4880r L0000000000000040 [4880r,4928r:0)  0 at 4880r weight:0.000000e+00
		merge %246:0 at 4928r into %242:0 at 4880r --> @4880r
		joined lanes: 0000000000000040 [4880r,5024r:0)  0 at 4880r
	Joined SubRanges %242 [4880r,5120r:0)  0 at 4880r L0000000000000002 [4880r,5120r:0)  0 at 4880r L0000000000000040 [4880r,5024r:0)  0 at 4880r weight:0.000000e+00
		Expecting instruction removal at 4928r
		erased:	4928r	%246:vsrc = COPY %242.sub_vsx1:vsrprc
		updated: 4992B	%250:vsrc = contract nofpexcept XVMADDADP %250:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %216:vsrc, implicit $rm
		updated: 5024B	%252:vsrc = contract nofpexcept XVMADDADP %252:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
	Success: %246:sub_vsx1 -> %242
	Result = %242 [4880r,5120r:0)  0 at 4880r L0000000000000002 [4880r,5120r:0)  0 at 4880r L0000000000000040 [4880r,5024r:0)  0 at 4880r weight:0.000000e+00
4944B	%247:vsrc = COPY %244.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %247 in %244:sub_vsx0
		RHS = %247 [4944r,5152r:0)  0 at 4944r weight:0.000000e+00
		LHS = %244 [4896r,4960r:0)  0 at 4896r L0000000000000002 [4896r,4944r:0)  0 at 4896r L0000000000000040 [4896r,4960r:0)  0 at 4896r weight:0.000000e+00
		merge %247:0 at 4944r into %244:0 at 4896r --> @4896r
		LHST = %244 %244 [4896r,4960r:0)  0 at 4896r L0000000000000002 [4896r,4944r:0)  0 at 4896r L0000000000000040 [4896r,4960r:0)  0 at 4896r weight:0.000000e+00
		merge %247:0 at 4944r into %244:0 at 4896r --> @4896r
		joined lanes: 0000000000000002 [4896r,5152r:0)  0 at 4896r
	Joined SubRanges %244 [4896r,4960r:0)  0 at 4896r L0000000000000002 [4896r,5152r:0)  0 at 4896r L0000000000000040 [4896r,4960r:0)  0 at 4896r weight:0.000000e+00
		Expecting instruction removal at 4944r
		erased:	4944r	%247:vsrc = COPY %244.sub_vsx0:vsrprc
		updated: 5152B	%258:vsrc = contract nofpexcept XVMADDADP %258:vsrc(tied-def 0), %244.sub_vsx0:vsrprc, %241:vsrc, implicit $rm
	Success: %247:sub_vsx0 -> %244
	Result = %244 [4896r,5152r:0)  0 at 4896r L0000000000000002 [4896r,5152r:0)  0 at 4896r L0000000000000040 [4896r,4960r:0)  0 at 4896r weight:0.000000e+00
4960B	%248:vsrc = COPY %244.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %248 in %244:sub_vsx1
		RHS = %248 [4960r,5056r:0)  0 at 4960r weight:0.000000e+00
		LHS = %244 [4896r,5152r:0)  0 at 4896r L0000000000000002 [4896r,5152r:0)  0 at 4896r L0000000000000040 [4896r,4960r:0)  0 at 4896r weight:0.000000e+00
		merge %248:0 at 4960r into %244:0 at 4896r --> @4896r
		LHST = %244 %244 [4896r,5152r:0)  0 at 4896r L0000000000000002 [4896r,5152r:0)  0 at 4896r L0000000000000040 [4896r,4960r:0)  0 at 4896r weight:0.000000e+00
		merge %248:0 at 4960r into %244:0 at 4896r --> @4896r
		joined lanes: 0000000000000040 [4896r,5056r:0)  0 at 4896r
	Joined SubRanges %244 [4896r,5152r:0)  0 at 4896r L0000000000000002 [4896r,5152r:0)  0 at 4896r L0000000000000040 [4896r,5056r:0)  0 at 4896r weight:0.000000e+00
		Expecting instruction removal at 4960r
		erased:	4960r	%248:vsrc = COPY %244.sub_vsx1:vsrprc
		updated: 5056B	%253:vsrc = contract nofpexcept XVMADDADP %253:vsrc(tied-def 0), %244.sub_vsx1:vsrprc, %237:vsrc, implicit $rm
	Success: %248:sub_vsx1 -> %244
	Result = %244 [4896r,5152r:0)  0 at 4896r L0000000000000002 [4896r,5152r:0)  0 at 4896r L0000000000000040 [4896r,5056r:0)  0 at 4896r weight:0.000000e+00
4976B	%250:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %250 in %290
		RHS = %250 [4976r,4992r:0)[4992r,5072r:1)  0 at 4976r 1 at 4992r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4976r:30)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r weight:0.000000e+00
		merge %250:0 at 4976r into %290:30 at 4736r --> @4736r
		erased:	4976r	%250:vsrc = COPY %290:vsrc
		updated: 4992B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %216:vsrc, implicit $rm
		updated: 5072B	%255:vsrc = COPY %290:vsrc
	Success: %250 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5072r:31)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r weight:0.000000e+00
5008B	%252:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %252 in %289
		RHS = %252 [5008r,5024r:0)[5024r,5104r:1)  0 at 5008r 1 at 5024r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5008r:30)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r weight:0.000000e+00
		merge %252:0 at 5008r into %289:30 at 4768r --> @4768r
		erased:	5008r	%252:vsrc = COPY %289:vsrc
		updated: 5024B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
		updated: 5104B	%257:vsrc = COPY %289:vsrc
	Success: %252 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5104r:31)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r weight:0.000000e+00
5040B	%253:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %253 in %288
		RHS = %253 [5040r,5056r:0)[5056r,5136r:1)  0 at 5040r 1 at 5056r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5040r:30)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r weight:0.000000e+00
		merge %253:0 at 5040r into %288:30 at 4800r --> @4800r
		erased:	5040r	%253:vsrc = COPY %288:vsrc
		updated: 5056B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %244.sub_vsx1:vsrprc, %237:vsrc, implicit $rm
		updated: 5136B	%258:vsrc = COPY %288:vsrc
	Success: %253 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5136r:31)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r weight:0.000000e+00
5072B	%255:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %255 in %290
		RHS = %255 [5072r,5088r:0)[5088r,5296r:1)  0 at 5072r 1 at 5088r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5072r:31)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r weight:0.000000e+00
		merge %255:0 at 5072r into %290:31 at 4992r --> @4992r
		erased:	5072r	%255:vsrc = COPY %290:vsrc
		updated: 5088B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %235:vsrc, implicit $rm
		updated: 5296B	%271:vsrc = COPY %290:vsrc
	Success: %255 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5296r:32)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r weight:0.000000e+00
5104B	%257:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %257 in %289
		RHS = %257 [5104r,5120r:0)[5120r,5328r:1)  0 at 5104r 1 at 5120r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5104r:31)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r weight:0.000000e+00
		merge %257:0 at 5104r into %289:31 at 5024r --> @5024r
		erased:	5104r	%257:vsrc = COPY %289:vsrc
		updated: 5120B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %237:vsrc, implicit $rm
		updated: 5328B	%272:vsrc = COPY %289:vsrc
	Success: %257 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5328r:32)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r weight:0.000000e+00
5136B	%258:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %258 in %288
		RHS = %258 [5136r,5152r:0)[5152r,5360r:1)  0 at 5136r 1 at 5152r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5136r:31)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r weight:0.000000e+00
		merge %258:0 at 5136r into %288:31 at 5056r --> @5056r
		erased:	5136r	%258:vsrc = COPY %288:vsrc
		updated: 5152B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %244.sub_vsx0:vsrprc, %241:vsrc, implicit $rm
		updated: 5360B	%273:vsrc = COPY %288:vsrc
	Success: %258 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5152r:31)[5152r,5360r:32)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5152r weight:0.000000e+00
5264B	%269:vsrc = COPY %266.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %269 in %266:sub_vsx0
		RHS = %269 [5264r,5440r:0)  0 at 5264r weight:0.000000e+00
		LHS = %266 [5232r,5264r:0)  0 at 5232r L0000000000000002 [5232r,5264r:0)  0 at 5232r L0000000000000040 [5232r,5232d:0)  0 at 5232r weight:0.000000e+00
		merge %269:0 at 5264r into %266:0 at 5232r --> @5232r
		LHST = %266 %266 [5232r,5264r:0)  0 at 5232r L0000000000000002 [5232r,5264r:0)  0 at 5232r L0000000000000040 [5232r,5232d:0)  0 at 5232r weight:0.000000e+00
		merge %269:0 at 5264r into %266:0 at 5232r --> @5232r
		joined lanes: 0000000000000002 [5232r,5440r:0)  0 at 5232r
	Joined SubRanges %266 [5232r,5264r:0)  0 at 5232r L0000000000000002 [5232r,5440r:0)  0 at 5232r L0000000000000040 [5232r,5232d:0)  0 at 5232r weight:0.000000e+00
		Expecting instruction removal at 5264r
		erased:	5264r	%269:vsrc = COPY %266.sub_vsx0:vsrprc
		updated: 5408B	%18:vsrc = contract nofpexcept XVMADDADP %18:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %260:vsrc, implicit $rm
		updated: 5440B	%19:vsrc = contract nofpexcept XVMADDADP %19:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %262:vsrc, implicit $rm
	Success: %269:sub_vsx0 -> %266
	Result = %266 [5232r,5440r:0)  0 at 5232r L0000000000000002 [5232r,5440r:0)  0 at 5232r L0000000000000040 [5232r,5232d:0)  0 at 5232r weight:0.000000e+00
5280B	%270:vsrc = COPY %268.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %270 in %268:sub_vsx0
		RHS = %270 [5280r,5472r:0)  0 at 5280r weight:0.000000e+00
		LHS = %268 [5248r,5280r:0)  0 at 5248r L0000000000000002 [5248r,5280r:0)  0 at 5248r L0000000000000040 [5248r,5248d:0)  0 at 5248r weight:0.000000e+00
		merge %270:0 at 5280r into %268:0 at 5248r --> @5248r
		LHST = %268 %268 [5248r,5280r:0)  0 at 5248r L0000000000000002 [5248r,5280r:0)  0 at 5248r L0000000000000040 [5248r,5248d:0)  0 at 5248r weight:0.000000e+00
		merge %270:0 at 5280r into %268:0 at 5248r --> @5248r
		joined lanes: 0000000000000002 [5248r,5472r:0)  0 at 5248r
	Joined SubRanges %268 [5248r,5280r:0)  0 at 5248r L0000000000000002 [5248r,5472r:0)  0 at 5248r L0000000000000040 [5248r,5248d:0)  0 at 5248r weight:0.000000e+00
		Expecting instruction removal at 5280r
		erased:	5280r	%270:vsrc = COPY %268.sub_vsx0:vsrprc
		updated: 5472B	%20:vsrc = contract nofpexcept XVMADDADP %20:vsrc(tied-def 0), %268.sub_vsx0:vsrprc, %265:vsrc, implicit $rm
	Success: %270:sub_vsx0 -> %268
	Result = %268 [5248r,5472r:0)  0 at 5248r L0000000000000002 [5248r,5472r:0)  0 at 5248r L0000000000000040 [5248r,5248d:0)  0 at 5248r weight:0.000000e+00
5296B	%271:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %271 in %290
		RHS = %271 [5296r,5312r:0)[5312r,5392r:1)  0 at 5296r 1 at 5312r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5296r:32)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r weight:0.000000e+00
		merge %271:0 at 5296r into %290:32 at 5088r --> @5088r
		erased:	5296r	%271:vsrc = COPY %290:vsrc
		updated: 5312B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %239:vsrc, %50:vsrc, implicit $rm
		updated: 5392B	%18:vsrc = COPY %290:vsrc
	Success: %271 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5312r:32)[5312r,5392r:33)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r 33 at 5312r weight:0.000000e+00
5328B	%272:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %272 in %289
		RHS = %272 [5328r,5344r:0)[5344r,5424r:1)  0 at 5328r 1 at 5344r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5328r:32)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r weight:0.000000e+00
		merge %272:0 at 5328r into %289:32 at 5120r --> @5120r
		erased:	5328r	%272:vsrc = COPY %289:vsrc
		updated: 5344B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %241:vsrc, %50:vsrc, implicit $rm
		updated: 5424B	%19:vsrc = COPY %289:vsrc
	Success: %272 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5344r:32)[5344r,5424r:33)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r 33 at 5344r weight:0.000000e+00
5360B	%273:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %273 in %288
		RHS = %273 [5360r,5376r:0)[5376r,5456r:1)  0 at 5360r 1 at 5376r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5152r:31)[5152r,5360r:32)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5152r weight:0.000000e+00
		merge %273:0 at 5360r into %288:32 at 5152r --> @5152r
		erased:	5360r	%273:vsrc = COPY %288:vsrc
		updated: 5376B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %262:vsrc, %50:vsrc, implicit $rm
		updated: 5456B	%20:vsrc = COPY %288:vsrc
	Success: %273 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5152r:31)[5152r,5376r:32)[5376r,5456r:33)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5152r 33 at 5376r weight:0.000000e+00
5392B	%18:vsrc = COPY %290:vsrc
	Considering merging to VSRC with %18 in %290
		RHS = %18 [5392r,5408r:0)[5408r,5600r:1)  0 at 5392r 1 at 5408r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5312r:32)[5312r,5392r:33)[5600r,5664B:1)  0 at 1136r 1 at 5600r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r 33 at 5312r weight:0.000000e+00
		merge %290:1 at 5600r into %18:1 at 5408r --> @5408r
		merge %18:0 at 5392r into %290:33 at 5312r --> @5312r
		erased:	5600r	%290:vsrc = COPY %18:vsrc
		erased:	5392r	%18:vsrc = COPY %290:vsrc
		updated: 5408B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %260:vsrc, implicit $rm
	Success: %18 -> %290
	Result = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5312r:32)[5312r,5408r:33)[5408r,5664B:1)  0 at 1136r 1 at 5408r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r 33 at 5312r weight:0.000000e+00
5424B	%19:vsrc = COPY %289:vsrc
	Considering merging to VSRC with %19 in %289
		RHS = %19 [5424r,5440r:0)[5440r,5584r:1)  0 at 5424r 1 at 5440r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5344r:32)[5344r,5424r:33)[5584r,5664B:1)  0 at 1120r 1 at 5584r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r 33 at 5344r weight:0.000000e+00
		merge %289:1 at 5584r into %19:1 at 5440r --> @5440r
		merge %19:0 at 5424r into %289:33 at 5344r --> @5344r
		erased:	5584r	%289:vsrc = COPY %19:vsrc
		erased:	5424r	%19:vsrc = COPY %289:vsrc
		updated: 5440B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %262:vsrc, implicit $rm
	Success: %19 -> %289
	Result = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5344r:32)[5344r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r 33 at 5344r weight:0.000000e+00
5456B	%20:vsrc = COPY %288:vsrc
	Considering merging to VSRC with %20 in %288
		RHS = %20 [5456r,5472r:0)[5472r,5568r:1)  0 at 5456r 1 at 5472r weight:0.000000e+00
		LHS = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5152r:31)[5152r,5376r:32)[5376r,5456r:33)[5568r,5664B:1)  0 at 1104r 1 at 5568r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5152r 33 at 5376r weight:0.000000e+00
		merge %288:1 at 5568r into %20:1 at 5472r --> @5472r
		merge %20:0 at 5456r into %288:33 at 5376r --> @5376r
		erased:	5568r	%288:vsrc = COPY %20:vsrc
		erased:	5456r	%20:vsrc = COPY %288:vsrc
		updated: 5472B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %268.sub_vsx0:vsrprc, %265:vsrc, implicit $rm
	Success: %20 -> %288
	Result = %288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5152r:31)[5152r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5152r 33 at 5376r weight:0.000000e+00
5520B	%285:g8rc_and_g8rc_nox0 = COPY %22:g8rc
	Considering merging to G8RC_and_G8RC_NOX0 with %22 in %285
		RHS = %22 [5504r,5520r:0)  0 at 5504r weight:0.000000e+00
		LHS = %285 [1056r,1168B:0)[1168B,5504r:2)[5520r,5664B:1)  0 at 1056r 1 at 5520r 2 at 1168B-phi weight:0.000000e+00
		merge %285:1 at 5520r into %22:0 at 5504r --> @5504r
		erased:	5520r	%285:g8rc_and_g8rc_nox0 = COPY %22:g8rc
		updated: 5504B	%285:g8rc_and_g8rc_nox0 = ADDI8 %285:g8rc_and_g8rc_nox0, 512
	Success: %22 -> %285
	Result = %285 [1056r,1168B:0)[1168B,5504r:1)[5504r,5664B:2)  0 at 1056r 1 at 1168B-phi 2 at 5504r weight:0.000000e+00
5536B	%286:g8rc_and_g8rc_nox0 = COPY %21:g8rc
	Considering merging to G8RC_and_G8RC_NOX0 with %21 in %286
		RHS = %21 [5488r,5536r:0)  0 at 5488r weight:0.000000e+00
		LHS = %286 [1072r,1168B:0)[1168B,5488r:2)[5536r,5664B:1)  0 at 1072r 1 at 5536r 2 at 1168B-phi weight:0.000000e+00
		merge %286:1 at 5536r into %21:0 at 5488r --> @5488r
		erased:	5536r	%286:g8rc_and_g8rc_nox0 = COPY %21:g8rc
		updated: 5488B	%286:g8rc_and_g8rc_nox0 = nsw ADDI8 %286:g8rc_and_g8rc_nox0, 512
	Success: %21 -> %286
	Result = %286 [1072r,1168B:0)[1168B,5488r:1)[5488r,5664B:2)  0 at 1072r 1 at 1168B-phi 2 at 5488r weight:0.000000e+00
5552B	%287:vsrc = COPY %17:vsrc
	Considering merging to VSRC with %17 in %287
		RHS = %17 [5200r,5552r:0)  0 at 5200r weight:0.000000e+00
		LHS = %287 [1088r,1168B:0)[1168B,1328r:2)[5552r,5664B:1)  0 at 1088r 1 at 5552r 2 at 1168B-phi weight:0.000000e+00
		merge %287:1 at 5552r into %17:0 at 5200r --> @5200r
		erased:	5552r	%287:vsrc = COPY %17:vsrc
		updated: 5200B	%287:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %263:g8rc :: (load 8 from %ir.scevgep93.cast)
	Success: %17 -> %287
	Result = %287 [1088r,1168B:0)[1168B,1328r:2)[5200r,5664B:1)  0 at 1088r 1 at 5200r 2 at 1168B-phi weight:0.000000e+00
5616B	%291:g8rc_and_g8rc_nox0 = COPY %16:g8rc
	Considering merging to G8RC_and_G8RC_NOX0 with %16 in %291
		RHS = %16 [1296r,5616r:0)  0 at 1296r weight:0.000000e+00
		LHS = %291 [1152r,1168B:0)[1168B,5216r:2)[5616r,5664B:1)  0 at 1152r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
		merge %291:1 at 5616r into %16:0 at 1296r --> @1296r
		interference at %16:0 at 1296r
	Interference!
bb:
16B	%25:g8rc_and_g8rc_nox0 = COPY $x4
	Considering merging %25 with $x4
	Can only merge into reserved registers.
32B	%24:g8rc = COPY $x3
	Considering merging %24 with $x3
	Can only merge into reserved registers.
bb9.preheader:
bb421:
144B	%35:vsrc = COPY %34.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %35 in %34:sub_vsx1
		RHS = %35 [144r,160r:0)  0 at 144r weight:0.000000e+00
		LHS = %34 [128r,176r:0)  0 at 128r L0000000000000040 [128r,144r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r weight:0.000000e+00
		merge %35:0 at 144r into %34:0 at 128r --> @128r
		LHST = %34 %34 [128r,176r:0)  0 at 128r L0000000000000040 [128r,144r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r weight:0.000000e+00
		merge %35:0 at 144r into %34:0 at 128r --> @128r
		joined lanes: 0000000000000040 [128r,160r:0)  0 at 128r
	Joined SubRanges %34 [128r,176r:0)  0 at 128r L0000000000000040 [128r,160r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r weight:0.000000e+00
		Expecting instruction removal at 144r
		erased:	144r	%35:vsrc = COPY %34.sub_vsx1:vsrprc
		updated: 160B	undef %36.sub_vsx1:vsrprc = COPY %34.sub_vsx1:vsrprc
	Success: %35:sub_vsx1 -> %34
	Result = %34 [128r,176r:0)  0 at 128r L0000000000000040 [128r,160r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r weight:0.000000e+00
160B	undef %36.sub_vsx1:vsrprc = COPY %34.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %34 in %36
		RHS = %34 [128r,176r:0)  0 at 128r L0000000000000040 [128r,160r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r weight:0.000000e+00
		LHS = %36 [160r,192r:0)  0 at 160r L0000000000000040 [160r,192r:0)  0 at 160r weight:0.000000e+00
		merge %36:0 at 160r into %34:0 at 128r --> @128r
		LHST = %36 %36 [160r,192r:0)  0 at 160r L0000000000000040 [160r,192r:0)  0 at 160r weight:0.000000e+00
		merge %36:0 at 160r into %34:0 at 128r --> @128r
		joined lanes: 0000000000000040 [128r,192r:0)  0 at 128r
	Joined SubRanges %36 [160r,192r:0)  0 at 160r L0000000000000002 [128r,176r:0)  0 at 128r L0000000000000040 [128r,192r:0)  0 at 128r weight:0.000000e+00
		Expecting instruction removal at 160r
		erased:	160r	undef %36.sub_vsx1:vsrprc = COPY %34.sub_vsx1:vsrprc
		updated: 128B	%36:vsrprc = LXVP 0, %33:g8rc_and_g8rc_nox0 :: (load 32 from constant-pool)
		updated: 176B	%38:vsrc = COPY %36.sub_vsx0:vsrprc
	Success: %34 -> %36
	Result = %36 [128r,192r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r L0000000000000040 [128r,192r:0)  0 at 128r weight:0.000000e+00
176B	%38:vsrc = COPY %36.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %38 in %36:sub_vsx0
		RHS = %38 [176r,208r:0)  0 at 176r weight:0.000000e+00
		LHS = %36 [128r,192r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r L0000000000000040 [128r,192r:0)  0 at 128r weight:0.000000e+00
		merge %38:0 at 176r into %36:0 at 128r --> @128r
		LHST = %36 %36 [128r,192r:0)  0 at 128r L0000000000000002 [128r,176r:0)  0 at 128r L0000000000000040 [128r,192r:0)  0 at 128r weight:0.000000e+00
		merge %38:0 at 176r into %36:0 at 128r --> @128r
		joined lanes: 0000000000000002 [128r,208r:0)  0 at 128r
	Joined SubRanges %36 [128r,192r:0)  0 at 128r L0000000000000002 [128r,208r:0)  0 at 128r L0000000000000040 [128r,192r:0)  0 at 128r weight:0.000000e+00
		Expecting instruction removal at 176r
		erased:	176r	%38:vsrc = COPY %36.sub_vsx0:vsrprc
		updated: 208B	%39.sub_vsx0:vsrprc = COPY %36.sub_vsx0:vsrprc
	Success: %38:sub_vsx0 -> %36
	Result = %36 [128r,208r:0)  0 at 128r L0000000000000002 [128r,208r:0)  0 at 128r L0000000000000040 [128r,192r:0)  0 at 128r weight:0.000000e+00
192B	%39:vsrprc = COPY %36:vsrprc
	Considering merging to VSRpRC with %36 in %39
		RHS = %36 [128r,208r:0)  0 at 128r L0000000000000002 [128r,208r:0)  0 at 128r L0000000000000040 [128r,192r:0)  0 at 128r weight:0.000000e+00
		LHS = %39 [192r,208r:0)[208r,224r:1)  0 at 192r 1 at 208r L0000000000000002 [192r,192d:0)[208r,224r:1)  0 at 192r 1 at 208r L0000000000000040 [192r,192d:0)  0 at 192r weight:0.000000e+00
		merge %39:0 at 192r into %36:0 at 128r --> @128r
		merge %39:1 at 208r into %36:0 at 128r --> @128r
		LHST = %39 %39 [192r,208r:0)[208r,224r:1)  0 at 192r 1 at 208r L0000000000000002 [192r,192d:0)[208r,224r:1)  0 at 192r 1 at 208r L0000000000000040 [192r,192d:0)  0 at 192r weight:0.000000e+00
		merge %39:0 at 192r into %36:0 at 128r --> @128r
		merge %39:1 at 208r into %36:0 at 128r --> @128r
		joined lanes: 0000000000000002 [128r,224r:0)  0 at 128r
		merge %39:0 at 192r into %36:0 at 128r --> @128r
		joined lanes: 0000000000000040 [128r,192d:0)  0 at 128r
	Joined SubRanges %39 [192r,208r:0)[208r,224r:1)  0 at 192r 1 at 208r L0000000000000002 [128r,224r:0)  0 at 128r L0000000000000040 [128r,192d:0)  0 at 128r weight:0.000000e+00
		Expecting instruction removal at 192r
		Dead uses at sublane 0000000000000040 at 192r
		Expecting instruction removal at 208r
		erased:	192r	%39:vsrprc = COPY %36:vsrprc
		erased:	208r	%39.sub_vsx0:vsrprc = COPY %36.sub_vsx0:vsrprc
		updated: 128B	%39:vsrprc = LXVP 0, %33:g8rc_and_g8rc_nox0 :: (load 32 from constant-pool)
Shrink LaneUses (Lane 0000000000000040)
Shrink:  L0000000000000040 [128r,192d:0)  0 at 128r
Shrunk:  L0000000000000040 [128r,128d:0)  0 at 128r
	Success: %36 -> %39
	Result = %39 [128r,224r:0)  0 at 128r L0000000000000002 [128r,224r:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
224B	%40:vsrc = COPY %39.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %40 in %39:sub_vsx0
		RHS = %40 [224r,240r:0)  0 at 224r weight:0.000000e+00
		LHS = %39 [128r,224r:0)  0 at 128r L0000000000000002 [128r,224r:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
		merge %40:0 at 224r into %39:0 at 128r --> @128r
		LHST = %39 %39 [128r,224r:0)  0 at 128r L0000000000000002 [128r,224r:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
		merge %40:0 at 224r into %39:0 at 128r --> @128r
		joined lanes: 0000000000000002 [128r,240r:0)  0 at 128r
	Joined SubRanges %39 [128r,224r:0)  0 at 128r L0000000000000002 [128r,240r:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
		Expecting instruction removal at 224r
		erased:	224r	%40:vsrc = COPY %39.sub_vsx0:vsrprc
		updated: 240B	%41:vsrc = COPY %39.sub_vsx0:vsrprc
	Success: %40:sub_vsx0 -> %39
	Result = %39 [128r,240r:0)  0 at 128r L0000000000000002 [128r,240r:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
240B	%41:vsrc = COPY %39.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %41 in %39:sub_vsx0
		RHS = %41 [240r,5664B:0)  0 at 240r weight:0.000000e+00
		LHS = %39 [128r,240r:0)  0 at 128r L0000000000000002 [128r,240r:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
		merge %41:0 at 240r into %39:0 at 128r --> @128r
		LHST = %39 %39 [128r,240r:0)  0 at 128r L0000000000000002 [128r,240r:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
		merge %41:0 at 240r into %39:0 at 128r --> @128r
		joined lanes: 0000000000000002 [128r,5664B:0)  0 at 128r
	Joined SubRanges %39 [128r,240r:0)  0 at 128r L0000000000000002 [128r,5664B:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
		Expecting instruction removal at 240r
		erased:	240r	%41:vsrc = COPY %39.sub_vsx0:vsrprc
		updated: 1696B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %50:vsrc, implicit $rm
		updated: 1728B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %62:vsrc, implicit $rm
	Success: %41:sub_vsx0 -> %39
	Result = %39 [128r,5664B:0)  0 at 128r L0000000000000002 [128r,5664B:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
304B	%43:vsrc = COPY %42.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %43 in %42:sub_vsx0
		RHS = %43 [304r,352r:0)  0 at 304r weight:0.000000e+00
		LHS = %42 [288r,320r:0)  0 at 288r L0000000000000002 [288r,304r:0)  0 at 288r L0000000000000040 [288r,320r:0)  0 at 288r weight:0.000000e+00
		merge %43:0 at 304r into %42:0 at 288r --> @288r
		LHST = %42 %42 [288r,320r:0)  0 at 288r L0000000000000002 [288r,304r:0)  0 at 288r L0000000000000040 [288r,320r:0)  0 at 288r weight:0.000000e+00
		merge %43:0 at 304r into %42:0 at 288r --> @288r
		joined lanes: 0000000000000002 [288r,352r:0)  0 at 288r
	Joined SubRanges %42 [288r,320r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,320r:0)  0 at 288r weight:0.000000e+00
		Expecting instruction removal at 304r
		erased:	304r	%43:vsrc = COPY %42.sub_vsx0:vsrprc
		updated: 352B	%46:vsrc = COPY %42.sub_vsx0:vsrprc
	Success: %43:sub_vsx0 -> %42
	Result = %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,320r:0)  0 at 288r weight:0.000000e+00
320B	%44:vsrc = COPY %42.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %44 in %42:sub_vsx1
		RHS = %44 [320r,336r:0)  0 at 320r weight:0.000000e+00
		LHS = %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,320r:0)  0 at 288r weight:0.000000e+00
		merge %44:0 at 320r into %42:0 at 288r --> @288r
		LHST = %42 %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,320r:0)  0 at 288r weight:0.000000e+00
		merge %44:0 at 320r into %42:0 at 288r --> @288r
		joined lanes: 0000000000000040 [288r,336r:0)  0 at 288r
	Joined SubRanges %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,336r:0)  0 at 288r weight:0.000000e+00
		Expecting instruction removal at 320r
		erased:	320r	%44:vsrc = COPY %42.sub_vsx1:vsrprc
		updated: 336B	%45:vsrc = COPY %42.sub_vsx1:vsrprc
	Success: %44:sub_vsx1 -> %42
	Result = %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,336r:0)  0 at 288r weight:0.000000e+00
336B	%45:vsrc = COPY %42.sub_vsx1:vsrprc
	Considering merging to VSRpRC with %45 in %42:sub_vsx1
		RHS = %45 [336r,5664B:0)  0 at 336r weight:0.000000e+00
		LHS = %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,336r:0)  0 at 288r weight:0.000000e+00
		merge %45:0 at 336r into %42:0 at 288r --> @288r
		LHST = %42 %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,336r:0)  0 at 288r weight:0.000000e+00
		merge %45:0 at 336r into %42:0 at 288r --> @288r
		joined lanes: 0000000000000040 [288r,5664B:0)  0 at 288r
	Joined SubRanges %42 [288r,352r:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,5664B:0)  0 at 288r weight:0.000000e+00
		Expecting instruction removal at 336r
		erased:	336r	%45:vsrc = COPY %42.sub_vsx1:vsrprc
		updated: 1792B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %50:vsrc, implicit $rm
		updated: 1824B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %64:vsrc, implicit $rm
	Success: %45:sub_vsx1 -> %42
	Result = %42 [288r,5664B:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,5664B:0)  0 at 288r weight:0.000000e+00
352B	%46:vsrc = COPY %42.sub_vsx0:vsrprc
	Considering merging to VSRpRC with %46 in %42:sub_vsx0
		RHS = %46 [352r,5664B:0)  0 at 352r weight:0.000000e+00
		LHS = %42 [288r,5664B:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,5664B:0)  0 at 288r weight:0.000000e+00
		merge %46:0 at 352r into %42:0 at 288r --> @288r
		LHST = %42 %42 [288r,5664B:0)  0 at 288r L0000000000000002 [288r,352r:0)  0 at 288r L0000000000000040 [288r,5664B:0)  0 at 288r weight:0.000000e+00
		merge %46:0 at 352r into %42:0 at 288r --> @288r
		joined lanes: 0000000000000002 [288r,5664B:0)  0 at 288r
	Joined SubRanges %42 [288r,5664B:0)  0 at 288r L0000000000000002 [288r,5664B:0)  0 at 288r L0000000000000040 [288r,5664B:0)  0 at 288r weight:0.000000e+00
		Expecting instruction removal at 352r
		erased:	352r	%46:vsrc = COPY %42.sub_vsx0:vsrprc
		updated: 1888B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %50:vsrc, implicit $rm
		updated: 1920B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %50:vsrc, implicit $rm
	Success: %46:sub_vsx0 -> %42
	Result = %42 [288r,5664B:0)  0 at 288r L0000000000000002 [288r,5664B:0)  0 at 288r L0000000000000040 [288r,5664B:0)  0 at 288r weight:0.000000e+00
416B	%8:g8rc = COPY %25:g8rc_and_g8rc_nox0
	Considering merging to G8RC_and_G8RC_NOX0 with %25 in %8
		RHS = %25 [16r,416r:0)  0 at 16r weight:0.000000e+00
		LHS = %8 [416r,1152r:0)  0 at 416r weight:0.000000e+00
		merge %8:0 at 416r into %25:0 at 16r --> @16r
		erased:	416r	%8:g8rc = COPY %25:g8rc_and_g8rc_nox0
		updated: 16B	%8:g8rc_and_g8rc_nox0 = COPY $x4
		updated: 384B	%5:vsrc = LXVDSX %8:g8rc_and_g8rc_nox0, %47:g8rc :: (load 8 from %ir.4)
	Success: %25 -> %8
	Result = %8 [16r,1152r:0)  0 at 16r weight:0.000000e+00
480B	%51:vsrc = COPY %50:vsrc
	Considering merging to VSRC with %50 in %51
		RHS = %50 [464r,5664B:0)  0 at 464r weight:0.000000e+00
		LHS = %51 [480r,496r:0)  0 at 480r weight:0.000000e+00
		merge %51:0 at 480r into %50:0 at 464r --> @464r
		erased:	480r	%51:vsrc = COPY %50:vsrc
		updated: 464B	%51:vsrc = XXLXORz
		updated: 1328B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %287:vsrc, %51:vsrc, implicit $rm
		updated: 1360B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1392B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1424B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1456B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1488B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1600B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1632B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1696B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %51:vsrc, implicit $rm
		updated: 1760B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %64:vsrc, %51:vsrc, implicit $rm
		updated: 1792B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %51:vsrc, implicit $rm
		updated: 1856B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1888B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %51:vsrc, implicit $rm
		updated: 1920B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %51:vsrc, implicit $rm
		updated: 1952B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 1984B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %1:vsrc, %51:vsrc, implicit $rm
		updated: 2016B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2048B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2080B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2112B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2144B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2192B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %5:vsrc, %51:vsrc, implicit $rm
		updated: 2224B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2256B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2288B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2320B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2352B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2384B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %88:vsrc, %51:vsrc, implicit $rm
		updated: 2416B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2448B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2480B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2512B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2544B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2576B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2608B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2640B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2672B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2704B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2736B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2784B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2816B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2848B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %108:vsrc, %51:vsrc, implicit $rm
		updated: 2880B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2912B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %108:vsrc, %51:vsrc, implicit $rm
		updated: 2944B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 2992B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 3024B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 3056B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 3088B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 3120B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 3152B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %51:vsrc, %51:vsrc, implicit $rm
		updated: 3328B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %51:vsrc, implicit $rm
		updated: 3392B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %51:vsrc, implicit $rm
		updated: 3648B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %51:vsrc, implicit $rm
		updated: 4640B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %51:vsrc, implicit $rm
		updated: 4736B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %51:vsrc, implicit $rm
		updated: 5312B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %239:vsrc, %51:vsrc, implicit $rm
		updated: 5344B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %241:vsrc, %51:vsrc, implicit $rm
		updated: 5376B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %262:vsrc, %51:vsrc, implicit $rm
	Success: %50 -> %51
	Result = %51 [464r,5664B:0)  0 at 464r weight:0.000000e+00
496B	%31:vsrc = COPY %51:vsrc
	Considering merging to VSRC with %51 in %31
		RHS = %51 [464r,5664B:0)  0 at 464r weight:0.000000e+00
		LHS = %31 [496r,1136r:0)  0 at 496r weight:0.000000e+00
		merge %31:0 at 496r into %51:0 at 464r --> @464r
		erased:	496r	%31:vsrc = COPY %51:vsrc
		updated: 464B	%31:vsrc = XXLXORz
		updated: 1328B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %287:vsrc, %31:vsrc, implicit $rm
		updated: 1360B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1392B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1424B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1456B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1488B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1600B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1632B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1696B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 1760B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %64:vsrc, %31:vsrc, implicit $rm
		updated: 1792B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 1856B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1888B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 1920B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 1952B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1984B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %1:vsrc, %31:vsrc, implicit $rm
		updated: 2016B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2048B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2080B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2112B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2144B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2192B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %5:vsrc, %31:vsrc, implicit $rm
		updated: 2224B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2256B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2288B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2320B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2352B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2384B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %88:vsrc, %31:vsrc, implicit $rm
		updated: 2416B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2448B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2480B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2512B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2544B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2576B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2608B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2640B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2672B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2704B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2736B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2784B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2816B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2848B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %108:vsrc, %31:vsrc, implicit $rm
		updated: 2880B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2912B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %108:vsrc, %31:vsrc, implicit $rm
		updated: 2944B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2992B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 3024B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 3056B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 3088B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 3120B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 3152B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 3328B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 3392B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 3648B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 4640B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 4736B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 5312B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %239:vsrc, %31:vsrc, implicit $rm
		updated: 5344B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %241:vsrc, %31:vsrc, implicit $rm
		updated: 5376B	%288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %262:vsrc, %31:vsrc, implicit $rm
	Success: %51 -> %31
	Result = %31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
1056B	%285:g8rc_and_g8rc_nox0 = COPY %28:g8rc
	Considering merging to G8RC_and_G8RC_NOX0 with %28 in %285
		RHS = %28 [256r,1056r:0)  0 at 256r weight:0.000000e+00
		LHS = %285 [1056r,1168B:0)[1168B,5504r:1)[5504r,5664B:2)  0 at 1056r 1 at 1168B-phi 2 at 5504r weight:0.000000e+00
		merge %285:0 at 1056r into %28:0 at 256r --> @256r
		erased:	1056r	%285:g8rc_and_g8rc_nox0 = COPY %28:g8rc
		updated: 256B	%285:g8rc_and_g8rc_nox0 = LI8 0
		updated: 272B	%1:vsrc = LXVDSX $zero8, %285:g8rc_and_g8rc_nox0 :: (load 8 from `double* null`)
	Success: %28 -> %285
	Result = %285 [256r,1168B:0)[1168B,5504r:1)[5504r,5664B:2)  0 at 256r 1 at 1168B-phi 2 at 5504r weight:0.000000e+00
1120B	%289:vsrc = COPY %31:vsrc
	Considering merging to VSRC with %31 in %289
		RHS = %31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
		LHS = %289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5344r:32)[5344r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r 33 at 5344r weight:0.000000e+00
		merge %289:0 at 1120r into %31:0 at 464r --> @464r
		interference at %289:1 at 5440r
		updated: 1120B	%289:vsrc = XXLXORz
		updated: 5440B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %262:vsrc, implicit $rm
		updated: 5344B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %241:vsrc, %31:vsrc, implicit $rm
		updated: 5120B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %237:vsrc, implicit $rm
		updated: 5024B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
		updated: 4768B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
		updated: 4672B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %197:vsrc, implicit $rm
		updated: 4464B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %195:vsrc, implicit $rm
		updated: 4368B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %174:vsrc, implicit $rm
		updated: 4128B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %170:vsrc, implicit $rm
		updated: 4032B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %149:vsrc, implicit $rm
		updated: 3776B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %145:vsrc, implicit $rm
		updated: 3680B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %124:vsrc, implicit $rm
		updated: 3424B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %5:vsrc, implicit $rm
		updated: 3328B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 3120B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 3024B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2912B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %108:vsrc, %31:vsrc, implicit $rm
		updated: 2816B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2704B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2608B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2512B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2416B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2320B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2224B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2112B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2016B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1920B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 1824B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %64:vsrc, implicit $rm
		updated: 1728B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %62:vsrc, implicit $rm
		updated: 1632B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1456B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1360B	%289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
Remat: %289:vsrc = XXLXORz
Shrink: %31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
 live-in at 1168B
Shrunk: %31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
1136B	%290:vsrc = COPY %31:vsrc
	Considering merging to VSRC with %31 in %290
		RHS = %31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
		LHS = %290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5312r:32)[5312r,5408r:33)[5408r,5664B:1)  0 at 1136r 1 at 5408r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r 33 at 5312r weight:0.000000e+00
		merge %290:0 at 1136r into %31:0 at 464r --> @464r
		interference at %290:1 at 5408r
		updated: 1136B	%290:vsrc = XXLXORz
		updated: 5408B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %260:vsrc, implicit $rm
		updated: 5312B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %239:vsrc, %31:vsrc, implicit $rm
		updated: 5088B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %235:vsrc, implicit $rm
		updated: 4992B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %216:vsrc, implicit $rm
		updated: 4736B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 4640B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 4432B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %193:vsrc, implicit $rm
		updated: 4336B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %172:vsrc, implicit $rm
		updated: 4096B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %168:vsrc, implicit $rm
		updated: 4000B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %147:vsrc, implicit $rm
		updated: 3744B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %143:vsrc, implicit $rm
		updated: 3648B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 3392B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 3296B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %116:vsrc, implicit $rm
		updated: 3088B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2992B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2880B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2784B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2672B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2576B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2480B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2384B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %88:vsrc, %31:vsrc, implicit $rm
		updated: 2288B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 2192B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %5:vsrc, %31:vsrc, implicit $rm
		updated: 2080B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1984B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %1:vsrc, %31:vsrc, implicit $rm
		updated: 1888B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 1792B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
		updated: 1696B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
		updated: 1600B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1424B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
		updated: 1328B	%290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %287:vsrc, %31:vsrc, implicit $rm
Remat: %290:vsrc = XXLXORz
Shrink: %31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
 live-in at 1168B
Shrunk: %31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
1152B	%291:g8rc_and_g8rc_nox0 = COPY %8:g8rc_and_g8rc_nox0
	Considering merging to G8RC_and_G8RC_NOX0 with %8 in %291
		RHS = %8 [16r,1152r:0)  0 at 16r weight:0.000000e+00
		LHS = %291 [1152r,1168B:0)[1168B,5216r:2)[5616r,5664B:1)  0 at 1152r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
		merge %291:0 at 1152r into %8:0 at 16r --> @16r
		erased:	1152r	%291:g8rc_and_g8rc_nox0 = COPY %8:g8rc_and_g8rc_nox0
		updated: 16B	%291:g8rc_and_g8rc_nox0 = COPY $x4
		updated: 384B	%5:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %47:g8rc :: (load 8 from %ir.4)
	Success: %8 -> %291
	Result = %291 [16r,1168B:0)[1168B,5216r:2)[5616r,5664B:1)  0 at 16r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
5696B	%278:vrrc = COPY %276:vsrc
	Considering merging to VRRC with %276 in %278
		RHS = %276 [5680r,5696r:0)  0 at 5680r weight:0.000000e+00
		LHS = %278 [5696r,5712r:0)[5712r,5728r:1)  0 at 5696r 1 at 5712r weight:0.000000e+00
		merge %278:0 at 5696r into %276:0 at 5680r --> @5680r
		erased:	5696r	%278:vrrc = COPY %276:vsrc
AllocationOrder(VRRC) = [ $v2 $v3 $v4 $v5 $v0 $v1 $v6 $v7 $v8 $v9 $v10 $v11 $v12 $v13 $v14 $v15 $v16 $v17 $v18 $v19 $v31 $v30 $v29 $v28 $v27 $v26 $v25 $v24 $v23 $v22 $v21 $v20 ] (sub-class)
		updated: 5680B	%278:vrrc = XXLXORz
	Success: %276 -> %278
	Result = %278 [5680r,5712r:0)[5712r,5728r:1)  0 at 5680r 1 at 5712r weight:0.000000e+00
5728B	undef %283.sub_vsx0:vsrprc = COPY %278:vrrc
	Considering merging to VSRpRC_with_sub_64_in_VFRC with %278 in %283:sub_vsx0
		RHS = %278 [5680r,5712r:0)[5712r,5728r:1)  0 at 5680r 1 at 5712r weight:0.000000e+00
		LHS = %283 [5728r,5744r:0)  0 at 5728r L0000000000000002 [5728r,5744r:0)  0 at 5728r weight:0.000000e+00
		merge %283:0 at 5728r into %278:1 at 5712r --> @5712r
		LHST = %283 %283 [5728r,5744r:0)  0 at 5728r L0000000000000002 [5728r,5744r:0)  0 at 5728r weight:0.000000e+00
		merge %283:0 at 5728r into %278:1 at 5712r --> @5712r
		joined lanes: 0000000000000002 [5680r,5712r:1)[5712r,5744r:0)  0 at 5712r 1 at 5680r
	Joined SubRanges %283 [5728r,5744r:0)  0 at 5728r L0000000000000002 [5680r,5712r:1)[5712r,5744r:0)  0 at 5712r 1 at 5680r weight:0.000000e+00
		Expecting instruction removal at 5728r
		erased:	5728r	undef %283.sub_vsx0:vsrprc = COPY %278:vrrc
AllocationOrder(VSRpRC_with_sub_64_in_VFRC) = [ $vsrp17 $vsrp18 $vsrp16 $vsrp19 $vsrp20 $vsrp21 $vsrp22 $vsrp23 $vsrp24 $vsrp25 $vsrp31 $vsrp30 $vsrp29 $vsrp28 $vsrp27 $vsrp26 ] (sub-class)
		updated: 5680B	undef %283.sub_vsx0:vsrprc_with_sub_64_in_vfrc = XXLXORz
		updated: 5712B	%283.sub_vsx0:vsrprc_with_sub_64_in_vfrc = XXSPLTI32DX %283.sub_vsx0:vsrprc_with_sub_64_in_vfrc(tied-def 0), 0, 2146959360
	Success: %278:sub_vsx0 -> %283
	Result = %283 [5680r,5712r:1)[5712r,5744r:0)  0 at 5712r 1 at 5680r L0000000000000002 [5680r,5712r:1)[5712r,5744r:0)  0 at 5712r 1 at 5680r weight:0.000000e+00
5616B	%291:g8rc_and_g8rc_nox0 = COPY %16:g8rc
	Considering merging to G8RC_and_G8RC_NOX0 with %16 in %291
		RHS = %16 [1296r,5616r:0)  0 at 1296r weight:0.000000e+00
		LHS = %291 [16r,1168B:0)[1168B,5216r:2)[5616r,5664B:1)  0 at 16r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
		merge %291:1 at 5616r into %16:0 at 1296r --> @1296r
		interference at %16:0 at 1296r
	Interference!
Trying to inflate 2 regs.
%283 inflated to VSRpRC
********** INTERVALS **********
R3 [0B,32r:0)  0 at 0B-phi
R4 [0B,16r:0)  0 at 0B-phi
%1 [272r,5664B:0)  0 at 272r weight:0.000000e+00
%5 [384r,5664B:0)  0 at 384r weight:0.000000e+00
%6 [400r,5664B:0)  0 at 400r weight:0.000000e+00
%16 [1296r,5616r:0)  0 at 1296r weight:0.000000e+00
%24 [32r,5664B:0)  0 at 32r weight:0.000000e+00
%27 EMPTY weight:0.000000e+00
%31 [464r,5664B:0)  0 at 464r weight:0.000000e+00
%32 [96r,112r:0)  0 at 96r weight:0.000000e+00
%33 [112r,128r:0)  0 at 112r weight:0.000000e+00
%39 [128r,5664B:0)  0 at 128r L0000000000000002 [128r,5664B:0)  0 at 128r L0000000000000040 [128r,128d:0)  0 at 128r weight:0.000000e+00
%42 [288r,5664B:0)  0 at 288r L0000000000000002 [288r,5664B:0)  0 at 288r L0000000000000040 [288r,5664B:0)  0 at 288r weight:0.000000e+00
%47 [368r,384r:0)  0 at 368r weight:0.000000e+00
%48 EMPTY weight:0.000000e+00
%49 [432r,448r:0)  0 at 432r weight:0.000000e+00
%60 [1504r,5248r:0)  0 at 1504r weight:0.000000e+00
%61 [512r,5664B:0)  0 at 512r weight:0.000000e+00
%62 [1520r,1728r:0)  0 at 1520r weight:0.000000e+00
%63 [528r,5664B:0)  0 at 528r weight:0.000000e+00
%64 [1536r,1824r:0)  0 at 1536r weight:0.000000e+00
%65 [544r,5664B:0)  0 at 544r weight:0.000000e+00
%66 [1552r,1664r:0)  0 at 1552r L0000000000000040 [1552r,1664r:0)  0 at 1552r L0000000000000002 [1552r,1552d:0)  0 at 1552r weight:0.000000e+00
%87 [560r,5664B:0)  0 at 560r weight:0.000000e+00
%88 [2160r,2384r:0)  0 at 2160r weight:0.000000e+00
%107 [576r,5664B:0)  0 at 576r weight:0.000000e+00
%108 [2752r,2912r:0)  0 at 2752r weight:0.000000e+00
%115 [592r,5664B:0)  0 at 592r weight:0.000000e+00
%116 [2960r,3296r:0)  0 at 2960r weight:0.000000e+00
%123 [608r,5664B:0)  0 at 608r weight:0.000000e+00
%124 [3168r,3680r:0)  0 at 3168r weight:0.000000e+00
%125 [3184r,3424r:0)  0 at 3184r L0000000000000002 [3184r,3424r:0)  0 at 3184r L0000000000000040 [3184r,3328r:0)  0 at 3184r weight:0.000000e+00
%126 [624r,5664B:0)  0 at 624r weight:0.000000e+00
%127 [3200r,3456r:0)  0 at 3200r L0000000000000002 [3200r,3456r:0)  0 at 3200r L0000000000000040 [3200r,3360r:0)  0 at 3200r weight:0.000000e+00
%142 [640r,5664B:0)  0 at 640r weight:0.000000e+00
%143 [3472r,3744r:0)  0 at 3472r weight:0.000000e+00
%144 [656r,5664B:0)  0 at 656r weight:0.000000e+00
%145 [3488r,3776r:0)  0 at 3488r weight:0.000000e+00
%146 [672r,5664B:0)  0 at 672r weight:0.000000e+00
%147 [3504r,4000r:0)  0 at 3504r weight:0.000000e+00
%148 [688r,5664B:0)  0 at 688r weight:0.000000e+00
%149 [3520r,4032r:0)  0 at 3520r weight:0.000000e+00
%150 [3536r,3776r:0)  0 at 3536r L0000000000000002 [3536r,3776r:0)  0 at 3536r L0000000000000040 [3536r,3680r:0)  0 at 3536r weight:0.000000e+00
%151 [704r,5664B:0)  0 at 704r weight:0.000000e+00
%152 [3552r,3808r:0)  0 at 3552r L0000000000000002 [3552r,3808r:0)  0 at 3552r L0000000000000040 [3552r,3712r:0)  0 at 3552r weight:0.000000e+00
%167 [720r,5664B:0)  0 at 720r weight:0.000000e+00
%168 [3824r,4096r:0)  0 at 3824r weight:0.000000e+00
%169 [736r,5664B:0)  0 at 736r weight:0.000000e+00
%170 [3840r,4128r:0)  0 at 3840r weight:0.000000e+00
%171 [752r,5664B:0)  0 at 752r weight:0.000000e+00
%172 [3856r,4336r:0)  0 at 3856r weight:0.000000e+00
%173 [768r,5664B:0)  0 at 768r weight:0.000000e+00
%174 [3872r,4368r:0)  0 at 3872r weight:0.000000e+00
%175 [3888r,4128r:0)  0 at 3888r L0000000000000002 [3888r,4128r:0)  0 at 3888r L0000000000000040 [3888r,4032r:0)  0 at 3888r weight:0.000000e+00
%176 [784r,5664B:0)  0 at 784r weight:0.000000e+00
%177 [3904r,4160r:0)  0 at 3904r L0000000000000002 [3904r,4160r:0)  0 at 3904r L0000000000000040 [3904r,4064r:0)  0 at 3904r weight:0.000000e+00
%192 [800r,5664B:0)  0 at 800r weight:0.000000e+00
%193 [4176r,4432r:0)  0 at 4176r weight:0.000000e+00
%194 [816r,5664B:0)  0 at 816r weight:0.000000e+00
%195 [4192r,4464r:0)  0 at 4192r weight:0.000000e+00
%196 [832r,5664B:0)  0 at 832r weight:0.000000e+00
%197 [4208r,4672r:0)  0 at 4208r weight:0.000000e+00
%198 [4224r,4464r:0)  0 at 4224r L0000000000000002 [4224r,4464r:0)  0 at 4224r L0000000000000040 [4224r,4368r:0)  0 at 4224r weight:0.000000e+00
%199 [848r,5664B:0)  0 at 848r weight:0.000000e+00
%200 [4240r,4496r:0)  0 at 4240r L0000000000000002 [4240r,4496r:0)  0 at 4240r L0000000000000040 [4240r,4400r:0)  0 at 4240r weight:0.000000e+00
%215 [864r,5664B:0)  0 at 864r weight:0.000000e+00
%216 [4512r,4992r:0)  0 at 4512r weight:0.000000e+00
%217 [4528r,4768r:0)  0 at 4528r L0000000000000002 [4528r,4768r:0)  0 at 4528r L0000000000000040 [4528r,4672r:0)  0 at 4528r weight:0.000000e+00
%218 [880r,5664B:0)  0 at 880r weight:0.000000e+00
%219 [4544r,4800r:0)  0 at 4544r L0000000000000002 [4544r,4800r:0)  0 at 4544r L0000000000000040 [4544r,4704r:0)  0 at 4544r weight:0.000000e+00
%234 [896r,5664B:0)  0 at 896r weight:0.000000e+00
%235 [4816r,5088r:0)  0 at 4816r weight:0.000000e+00
%236 [912r,5664B:0)  0 at 912r weight:0.000000e+00
%237 [4832r,5120r:0)  0 at 4832r weight:0.000000e+00
%238 [928r,5664B:0)  0 at 928r weight:0.000000e+00
%239 [4848r,5312r:0)  0 at 4848r weight:0.000000e+00
%240 [944r,5664B:0)  0 at 944r weight:0.000000e+00
%241 [4864r,5344r:0)  0 at 4864r weight:0.000000e+00
%242 [4880r,5120r:0)  0 at 4880r L0000000000000002 [4880r,5120r:0)  0 at 4880r L0000000000000040 [4880r,5024r:0)  0 at 4880r weight:0.000000e+00
%243 [960r,5664B:0)  0 at 960r weight:0.000000e+00
%244 [4896r,5152r:0)  0 at 4896r L0000000000000002 [4896r,5152r:0)  0 at 4896r L0000000000000040 [4896r,5056r:0)  0 at 4896r weight:0.000000e+00
%259 [976r,5664B:0)  0 at 976r weight:0.000000e+00
%260 [5168r,5408r:0)  0 at 5168r weight:0.000000e+00
%261 [992r,5664B:0)  0 at 992r weight:0.000000e+00
%262 [5184r,5440r:0)  0 at 5184r weight:0.000000e+00
%263 [1008r,5664B:0)  0 at 1008r weight:0.000000e+00
%264 [1024r,5664B:0)  0 at 1024r weight:0.000000e+00
%265 [5216r,5472r:0)  0 at 5216r weight:0.000000e+00
%266 [5232r,5440r:0)  0 at 5232r L0000000000000002 [5232r,5440r:0)  0 at 5232r L0000000000000040 [5232r,5232d:0)  0 at 5232r weight:0.000000e+00
%267 [1040r,5664B:0)  0 at 1040r weight:0.000000e+00
%268 [5248r,5472r:0)  0 at 5248r L0000000000000002 [5248r,5472r:0)  0 at 5248r L0000000000000040 [5248r,5248d:0)  0 at 5248r weight:0.000000e+00
%283 [5680r,5712r:1)[5712r,5744r:0)  0 at 5712r 1 at 5680r L0000000000000002 [5680r,5712r:1)[5712r,5744r:0)  0 at 5712r 1 at 5680r weight:0.000000e+00
%284 EMPTY weight:0.000000e+00
%285 [256r,1168B:0)[1168B,5504r:1)[5504r,5664B:2)  0 at 256r 1 at 1168B-phi 2 at 5504r weight:0.000000e+00
%286 [1072r,1168B:0)[1168B,5488r:1)[5488r,5664B:2)  0 at 1072r 1 at 1168B-phi 2 at 5488r weight:0.000000e+00
%287 [1088r,1168B:0)[1168B,1328r:2)[5200r,5664B:1)  0 at 1088r 1 at 5200r 2 at 1168B-phi weight:0.000000e+00
%288 [1104r,1168B:0)[1168B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5152r:31)[5152r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1168B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5152r 33 at 5376r weight:0.000000e+00
%289 [1120r,1168B:0)[1168B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5344r:32)[5344r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1168B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r 33 at 5344r weight:0.000000e+00
%290 [1136r,1168B:0)[1168B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5312r:32)[5312r,5408r:33)[5408r,5664B:1)  0 at 1136r 1 at 5408r 2 at 1168B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r 33 at 5312r weight:0.000000e+00
%291 [16r,1168B:0)[1168B,5216r:2)[5616r,5664B:1)  0 at 16r 1 at 5616r 2 at 1168B-phi weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function test: NoPHIs, TracksLiveness, TiedOpsRewritten
Constant Pool:
  cp#0: zeroinitializer, align=32
Function Live Ins: $x3 in %24, $x4 in %25

0B	bb.0.bb:
	  successors: %bb.3(0x00000000), %bb.1(0x80000000); %bb.3(0.00%), %bb.1(100.00%)
	  liveins: $x3, $x4
16B	  %291:g8rc_and_g8rc_nox0 = COPY $x4
32B	  %24:g8rc = COPY $x3
48B	  BC undef %27:crbitrc, %bb.3
64B	  B %bb.1

80B	bb.1.bb9.preheader:
	; predecessors: %bb.0
	  successors: %bb.2(0x80000000); %bb.2(100.00%)

96B	  %32:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
112B	  %33:g8rc_and_g8rc_nox0 = ADDItocL %32:g8rc_and_g8rc_nox0, %const.0, implicit $x2
128B	  %39:vsrprc = LXVP 0, %33:g8rc_and_g8rc_nox0 :: (load 32 from constant-pool)
256B	  %285:g8rc_and_g8rc_nox0 = LI8 0
272B	  %1:vsrc = LXVDSX $zero8, %285:g8rc_and_g8rc_nox0 :: (load 8 from `double* null`)
288B	  %42:vsrprc = LXVP 0, $zero8
368B	  %47:g8rc = LI8 -8
384B	  %5:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %47:g8rc :: (load 8 from %ir.4)
400B	  %6:vsrc = LXVDSX $zero8, undef %48:g8rc :: (load 8 from `double* undef`)
432B	  %49:g8rc = LI8 1
448B	  MTCTR8loop %49:g8rc, implicit-def dead $ctr8
464B	  %31:vsrc = XXLXORz
512B	  %61:g8rc = LI8 512
528B	  %63:g8rc = LI8 528
544B	  %65:g8rc = LI8 56
560B	  %87:g8rc = LI8 616
576B	  %107:g8rc = LI8 704
592B	  %115:g8rc = LI8 744
608B	  %123:g8rc = LI8 784
624B	  %126:g8rc = LI8 312
640B	  %142:g8rc = LI8 792
656B	  %144:g8rc = LI8 800
672B	  %146:g8rc = LI8 808
688B	  %148:g8rc = LI8 816
704B	  %151:g8rc = LI8 344
720B	  %167:g8rc = LI8 824
736B	  %169:g8rc = LI8 832
752B	  %171:g8rc = LI8 840
768B	  %173:g8rc = LI8 848
784B	  %176:g8rc = LI8 376
800B	  %192:g8rc = LI8 856
816B	  %194:g8rc = LI8 864
832B	  %196:g8rc = LI8 880
848B	  %199:g8rc = LI8 408
864B	  %215:g8rc = LI8 904
880B	  %218:g8rc = LI8 440
896B	  %234:g8rc = LI8 920
912B	  %236:g8rc = LI8 928
928B	  %238:g8rc = LI8 936
944B	  %240:g8rc = LI8 944
960B	  %243:g8rc = LI8 472
976B	  %259:g8rc = LI8 952
992B	  %261:g8rc = LI8 960
1008B	  %263:g8rc = LI8 968
1024B	  %264:g8rc = LI8 976
1040B	  %267:g8rc = LI8 504
1072B	  %286:g8rc_and_g8rc_nox0 = IMPLICIT_DEF
1088B	  %287:vsrc = IMPLICIT_DEF
1104B	  %288:vsrc = IMPLICIT_DEF
1120B	  %289:vsrc = XXLXORz
1136B	  %290:vsrc = XXLXORz

1168B	bb.2.bb9:
	; predecessors: %bb.1, %bb.2
	  successors: %bb.2(0x80000000), %bb.3(0x00000000); %bb.2(100.00%), %bb.3(0.00%)

1296B	  %16:g8rc = ADDI8 %291:g8rc_and_g8rc_nox0, 512
1328B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %287:vsrc, %31:vsrc, implicit $rm
1360B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1392B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1424B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1456B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1488B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1504B	  %60:g8rc_and_g8rc_nox0 = ADD8 %24:g8rc, %285:g8rc_and_g8rc_nox0
1520B	  %62:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %61:g8rc :: (load 8 from %ir.i33.inc.cast)
1536B	  %64:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %63:g8rc :: (load 8 from %ir.scevgep123.cast)
1552B	  %66:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %65:g8rc
1600B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1632B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1664B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %66.sub_vsx1:vsrprc, %62:vsrc, implicit $rm
1696B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
1728B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %39.sub_vsx0:vsrprc, %62:vsrc, implicit $rm
1760B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %64:vsrc, %31:vsrc, implicit $rm
1792B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
1824B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx1:vsrprc, %64:vsrc, implicit $rm
1856B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1888B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
1920B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %42.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
1952B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
1984B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %1:vsrc, %31:vsrc, implicit $rm
2016B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2048B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2080B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2112B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2144B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2160B	  %88:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %87:g8rc :: (load 8 from %ir.scevgep111.cast)
2192B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %5:vsrc, %31:vsrc, implicit $rm
2224B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2256B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2288B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2320B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2352B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2384B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %88:vsrc, %31:vsrc, implicit $rm
2416B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2448B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2480B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2512B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2544B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2576B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2608B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2640B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2672B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2704B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2736B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2752B	  %108:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %107:g8rc :: (load 8 from %ir.scevgep126.cast)
2784B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2816B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2848B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %108:vsrc, %31:vsrc, implicit $rm
2880B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2912B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %108:vsrc, %31:vsrc, implicit $rm
2944B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
2960B	  %116:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %115:g8rc :: (load 8 from %ir.scevgep108.cast)
2992B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
3024B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
3056B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
3088B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
3120B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
3152B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
3168B	  %124:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %123:g8rc :: (load 8 from %ir.scevgep129.cast)
3184B	  %125:vsrprc = LXVP 288, %286:g8rc_and_g8rc_nox0
3200B	  %127:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %126:g8rc
3296B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %116:vsrc, implicit $rm
3328B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
3360B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %127.sub_vsx1:vsrprc, %5:vsrc, implicit $rm
3392B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
3424B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %125.sub_vsx0:vsrprc, %5:vsrc, implicit $rm
3456B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %127.sub_vsx0:vsrprc, %124:vsrc, implicit $rm
3472B	  %143:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %142:g8rc :: (load 8 from %ir.scevgep132.cast)
3488B	  %145:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %144:g8rc :: (load 8 from %ir.scevgep135.cast)
3504B	  %147:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %146:g8rc :: (load 8 from %ir.scevgep105.cast)
3520B	  %149:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %148:g8rc :: (load 8 from %ir.scevgep138.cast)
3536B	  %150:vsrprc = LXVP 320, %286:g8rc_and_g8rc_nox0
3552B	  %152:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %151:g8rc
3648B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
3680B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %124:vsrc, implicit $rm
3712B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %152.sub_vsx1:vsrprc, %145:vsrc, implicit $rm
3744B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %143:vsrc, implicit $rm
3776B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %145:vsrc, implicit $rm
3808B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %152.sub_vsx0:vsrprc, %149:vsrc, implicit $rm
3824B	  %168:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %167:g8rc :: (load 8 from %ir.scevgep141.cast)
3840B	  %170:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %169:g8rc :: (load 8 from %ir.scevgep144.cast)
3856B	  %172:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %171:g8rc :: (load 8 from %ir.scevgep102.cast)
3872B	  %174:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %173:g8rc :: (load 8 from %ir.scevgep147.cast)
3888B	  %175:vsrprc = LXVP 352, %286:g8rc_and_g8rc_nox0
3904B	  %177:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %176:g8rc
4000B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %147:vsrc, implicit $rm
4032B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %149:vsrc, implicit $rm
4064B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %177.sub_vsx1:vsrprc, %170:vsrc, implicit $rm
4096B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %168:vsrc, implicit $rm
4128B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %170:vsrc, implicit $rm
4160B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %177.sub_vsx0:vsrprc, %174:vsrc, implicit $rm
4176B	  %193:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %192:g8rc :: (load 8 from %ir.scevgep150.cast)
4192B	  %195:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %194:g8rc :: (load 8 from %ir.scevgep153.cast)
4208B	  %197:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %196:g8rc :: (load 8 from %ir.scevgep156.cast)
4224B	  %198:vsrprc = LXVP 384, %286:g8rc_and_g8rc_nox0
4240B	  %200:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %199:g8rc
4336B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %172:vsrc, implicit $rm
4368B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %174:vsrc, implicit $rm
4400B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %200.sub_vsx1:vsrprc, %195:vsrc, implicit $rm
4432B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %193:vsrc, implicit $rm
4464B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %195:vsrc, implicit $rm
4496B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %200.sub_vsx0:vsrprc, %197:vsrc, implicit $rm
4512B	  %216:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %215:g8rc :: (load 8 from %ir.scevgep99.cast)
4528B	  %217:vsrprc = LXVP 416, %286:g8rc_and_g8rc_nox0
4544B	  %219:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %218:g8rc
4640B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
4672B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %197:vsrc, implicit $rm
4704B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %219.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
4736B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
4768B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
4800B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %219.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
4816B	  %235:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %234:g8rc :: (load 8 from %ir.scevgep159.cast)
4832B	  %237:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %236:g8rc :: (load 8 from %ir.scevgep162.cast)
4848B	  %239:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %238:g8rc :: (load 8 from %ir.scevgep96.cast)
4864B	  %241:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %240:g8rc :: (load 8 from %ir.scevgep165.cast)
4880B	  %242:vsrprc = LXVP 448, %286:g8rc_and_g8rc_nox0
4896B	  %244:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %243:g8rc
4992B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %216:vsrc, implicit $rm
5024B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
5056B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %244.sub_vsx1:vsrprc, %237:vsrc, implicit $rm
5088B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %235:vsrc, implicit $rm
5120B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %237:vsrc, implicit $rm
5152B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %244.sub_vsx0:vsrprc, %241:vsrc, implicit $rm
5168B	  %260:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %259:g8rc :: (load 8 from %ir.scevgep117.cast)
5184B	  %262:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %261:g8rc :: (load 8 from %ir.scevgep114.cast)
5200B	  %287:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %263:g8rc :: (load 8 from %ir.scevgep93.cast)
5216B	  %265:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %264:g8rc :: (load 8 from %ir.uglygep8990.cast)
5232B	  %266:vsrprc = LXVP 480, %286:g8rc_and_g8rc_nox0
5248B	  %268:vsrprc = LXVPX %60:g8rc_and_g8rc_nox0, %267:g8rc
5312B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %239:vsrc, %31:vsrc, implicit $rm
5344B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %241:vsrc, %31:vsrc, implicit $rm
5376B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %262:vsrc, %31:vsrc, implicit $rm
5408B	  %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %260:vsrc, implicit $rm
5440B	  %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %266.sub_vsx0:vsrprc, %262:vsrc, implicit $rm
5472B	  %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %268.sub_vsx0:vsrprc, %265:vsrc, implicit $rm
5488B	  %286:g8rc_and_g8rc_nox0 = nsw ADDI8 %286:g8rc_and_g8rc_nox0, 512
5504B	  %285:g8rc_and_g8rc_nox0 = ADDI8 %285:g8rc_and_g8rc_nox0, 512
5616B	  %291:g8rc_and_g8rc_nox0 = COPY %16:g8rc
5632B	  BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8
5648B	  B %bb.3

5664B	bb.3.bb421:
	; predecessors: %bb.0, %bb.2

5680B	  undef %283.sub_vsx0:vsrprc = XXLXORz
5712B	  %283.sub_vsx0:vsrprc = XXSPLTI32DX %283.sub_vsx0:vsrprc(tied-def 0), 0, 2146959360
5744B	  STXVP %283:vsrprc, 0, undef %284:g8rc_and_g8rc_nox0

# End machine code for function test.

AllocationOrder(GPRC) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r0 $r30 $r29 $r28 $r27 $r26 $r25 $r24 $r23 $r22 $r21 $r20 $r19 $r18 $r17 $r16 $r15 $r14 $r31 ]
AllocationOrder(CARRYRC) = [ $carry $xer ]
AllocationOrder(VRSAVERC) = [ ]
AllocationOrder(ACCRC) = [ $acc0 $acc1 $acc2 $acc3 $acc4 $acc5 $acc6 $acc7 ]
AllocationOrder(ACCRC_with_sub_64_in_SPILLTOVSRRC) = [ $acc0 $acc1 $acc2 $acc3 ] (sub-class)
AllocationOrder(VSFRC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
AllocationOrder(SPILLTOVSRRC_and_VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 ] (sub-class)
AllocationOrder(CRBITRC) = [ $cr5lt $cr5gt $cr5eq $cr5un $cr6lt $cr6gt $cr6eq $cr6un $cr7lt $cr7gt $cr7eq $cr7un $cr1lt $cr1gt $cr1eq $cr1un $cr0lt $cr0gt $cr0eq $cr0un $cr2lt $cr2gt $cr2eq $cr2un $cr3lt $cr3gt $cr3eq $cr3un $cr4lt $cr4gt $cr4eq $cr4un ]
AllocationOrder(VSSRC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
AllocationOrder(F4RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ] (sub-class)
AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ] (sub-class)
AllocationOrder(GPRC) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r0 $r30 $r29 $r28 $r27 $r26 $r25 $r24 $r23 $r22 $r21 $r20 $r19 $r18 $r17 $r16 $r15 $r14 $r31 ]
AllocationOrder(SPILLTOVSRRC_and_VSFRC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 ] (sub-class)
AllocationOrder(SPILLTOVSRRC_and_VSFRC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 ] (sub-class)
AllocationOrder(SPILLTOVSRRC_and_VSFRC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 ] (sub-class)
AllocationOrder(VSSRC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
AllocationOrder(SPILLTOVSRRC) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x0 $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 $x31 ]
AllocationOrder(SPILLTOVSRRC) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x0 $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 $x31 ]
AllocationOrder(SPILLTOVSRRC) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x0 $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 $x31 ]
AllocationOrder(SPILLTOVSRRC) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x0 $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 $x31 ]
AllocationOrder(SPILLTOVSRRC) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x0 $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 $x31 ]
handleMove 1040B -> 1144B: %267:g8rc = LI8 504
     %267:	[1040r,5664B:0)  0 at 1040r
        -->	[1144r,5664B:0)  0 at 1144r
handleMove 1072B -> 1140B: %286:g8rc_and_g8rc_nox0 = IMPLICIT_DEF
     %286:	[1072r,1168B:0)[1168B,5488r:1)[5488r,5664B:2)  0 at 1072r 1 at 1168B-phi 2 at 5488r
        -->	[1140r,1168B:0)[1168B,5488r:1)[5488r,5664B:2)  0 at 1140r 1 at 1168B-phi 2 at 5488r
handleMove 1024B -> 1144B: %264:g8rc = LI8 976
     %264:	[1024r,5664B:0)  0 at 1024r
        -->	[1144r,5664B:0)  0 at 1144r
handleMove 1008B -> 1140B: %263:g8rc = LI8 968
     %263:	[1008r,5664B:0)  0 at 1008r
        -->	[1140r,5664B:0)  0 at 1140r
handleMove 992B -> 1144B: %261:g8rc = LI8 960
     %261:	[992r,5664B:0)  0 at 992r
        -->	[1144r,5664B:0)  0 at 1144r
handleMove 976B -> 1140B: %259:g8rc = LI8 952
     %259:	[976r,5664B:0)  0 at 976r
        -->	[1140r,5664B:0)  0 at 1140r
handleMove 128B -> 536B: %39:vsrprc = LXVP 0, %33:g8rc_and_g8rc_nox0 :: (load 32 from constant-pool)
     %39 L0000000000000002:	[128r,5664B:0)  0 at 128r
        -->	[536r,5664B:0)  0 at 536r
     %39 L0000000000000040:	[128r,128d:0)  0 at 128r
        -->	[536r,536d:0)  0 at 536r
     %39:	[128r,5664B:0)  0 at 128r
        -->	[536r,5664B:0)  0 at 536r
     %33:	[112r,128r:0)  0 at 112r
        -->	[112r,536r:0)  0 at 112r
handleMove 400B -> 440B: %6:vsrc = LXVDSX $zero8, undef %48:g8rc :: (load 8 from `double* undef`)
     %6:	[400r,5664B:0)  0 at 400r
        -->	[440r,5664B:0)  0 at 440r
handleMove 384B -> 436B: %5:vsrc = LXVDSX %291:g8rc_and_g8rc_nox0, %47:g8rc :: (load 8 from %ir.4)
     %5:	[384r,5664B:0)  0 at 384r
        -->	[436r,5664B:0)  0 at 436r
     %291:	[16r,1192B:0)[1192B,5216r:2)[5616r,5664B:1)  0 at 16r 1 at 5616r 2 at 1192B-phi
        -->	[16r,1192B:0)[1192B,5216r:2)[5616r,5664B:1)  0 at 16r 1 at 5616r 2 at 1192B-phi
     %47:	[368r,384r:0)  0 at 368r
        -->	[368r,436r:0)  0 at 368r
handleMove 1296B -> 5256B: %16:g8rc = ADDI8 %291:g8rc_and_g8rc_nox0, 512
     %16:	[1296r,5616r:0)  0 at 1296r
        -->	[5256r,5616r:0)  0 at 5256r
     %291:	[16r,1192B:0)[1192B,5216r:2)[5616r,5664B:1)  0 at 16r 1 at 5616r 2 at 1192B-phi
        -->	[16r,1192B:0)[1192B,5256r:2)[5616r,5664B:1)  0 at 16r 1 at 5616r 2 at 1192B-phi
handleMove 5152B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %244.sub_vsx0:vsrprc, %241:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5152r:31)[5152r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5152r 33 at 5376r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5252r:31)[5252r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5252r 33 at 5376r
     %244 L0000000000000002:	[4896r,5152r:0)  0 at 4896r
        -->	[4896r,5252r:0)  0 at 4896r
     %244:	[4896r,5152r:0)  0 at 4896r
        -->	[4896r,5252r:0)  0 at 4896r
     %241:	[4864r,5344r:0)  0 at 4864r
        -->	[4864r,5344r:0)  0 at 4864r
handleMove 5056B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %244.sub_vsx1:vsrprc, %237:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5056r:30)[5056r,5264r:31)[5264r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5056r 32 at 5264r 33 at 5376r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5256r:30)[5256r,5264r:31)[5264r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5256r 32 at 5264r 33 at 5376r
     %244 L0000000000000040:	[4896r,5056r:0)  0 at 4896r
        -->	[4896r,5256r:0)  0 at 4896r
     %244:	[4896r,5264r:0)  0 at 4896r
        -->	[4896r,5264r:0)  0 at 4896r
     %237:	[4832r,5120r:0)  0 at 4832r
        -->	[4832r,5256r:0)  0 at 4832r
handleMove 5120B -> 5252B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %237:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5120r:31)[5120r,5344r:32)[5344r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5120r 33 at 5344r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5252r:31)[5252r,5344r:32)[5344r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5252r 33 at 5344r
     %242 L0000000000000002:	[4880r,5120r:0)  0 at 4880r
        -->	[4880r,5252r:0)  0 at 4880r
     %242:	[4880r,5120r:0)  0 at 4880r
        -->	[4880r,5252r:0)  0 at 4880r
     %237:	[4832r,5256r:0)  0 at 4832r
        -->	[4832r,5256r:0)  0 at 4832r
handleMove 5024B -> 5256B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5024r:30)[5024r,5264r:31)[5264r,5344r:32)[5344r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5024r 32 at 5264r 33 at 5344r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5256r:30)[5256r,5264r:31)[5264r,5344r:32)[5344r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5256r 32 at 5264r 33 at 5344r
     %242 L0000000000000040:	[4880r,5024r:0)  0 at 4880r
        -->	[4880r,5256r:0)  0 at 4880r
     %242:	[4880r,5264r:0)  0 at 4880r
        -->	[4880r,5264r:0)  0 at 4880r
     %6:	[440r,5664B:0)  0 at 440r
        -->	[440r,5664B:0)  0 at 440r
handleMove 5088B -> 5252B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx0:vsrprc, %235:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5088r:31)[5088r,5320r:32)[5320r,5408r:33)[5408r,5664B:1)  0 at 1136r 1 at 5408r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5088r 33 at 5320r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5252r:31)[5252r,5320r:32)[5320r,5408r:33)[5408r,5664B:1)  0 at 1136r 1 at 5408r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5252r 33 at 5320r
     %242 L0000000000000002:	[4880r,5264r:0)  0 at 4880r
        -->	[4880r,5264r:0)  0 at 4880r
     %242:	[4880r,5264r:0)  0 at 4880r
        -->	[4880r,5264r:0)  0 at 4880r
     %235:	[4816r,5088r:0)  0 at 4816r
        -->	[4816r,5252r:0)  0 at 4816r
handleMove 4992B -> 5256B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %242.sub_vsx1:vsrprc, %216:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,4992r:30)[4992r,5264r:31)[5264r,5336r:32)[5336r,5408r:33)[5408r,5664B:1)  0 at 1136r 1 at 5408r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 4992r 32 at 5264r 33 at 5336r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,5256r:30)[5256r,5264r:31)[5264r,5336r:32)[5336r,5408r:33)[5408r,5664B:1)  0 at 1136r 1 at 5408r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 5256r 32 at 5264r 33 at 5336r
     %242 L0000000000000040:	[4880r,5272r:0)  0 at 4880r
        -->	[4880r,5272r:0)  0 at 4880r
     %242:	[4880r,5280r:0)  0 at 4880r
        -->	[4880r,5280r:0)  0 at 4880r
     %216:	[4512r,4992r:0)  0 at 4512r
        -->	[4512r,5256r:0)  0 at 4512r
handleMove 4800B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %219.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,4800r:29)[4800r,5288r:30)[5288r,5296r:31)[5296r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 4800r 31 at 5288r 32 at 5296r 33 at 5376r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,5252r:29)[5252r,5288r:30)[5288r,5296r:31)[5296r,5376r:32)[5376r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 5252r 31 at 5288r 32 at 5296r 33 at 5376r
     %219 L0000000000000002:	[4544r,4800r:0)  0 at 4544r
        -->	[4544r,5252r:0)  0 at 4544r
     %219:	[4544r,4800r:0)  0 at 4544r
        -->	[4544r,5252r:0)  0 at 4544r
     %6:	[440r,5664B:0)  0 at 440r
        -->	[440r,5664B:0)  0 at 440r
handleMove 4704B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %219.sub_vsx1:vsrprc, %6:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,4704r:28)[4704r,5264r:29)[5264r,5304r:30)[5304r,5312r:31)[5312r,5384r:32)[5384r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 4704r 30 at 5264r 31 at 5304r 32 at 5312r 33 at 5384r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,5256r:28)[5256r,5264r:29)[5264r,5304r:30)[5304r,5312r:31)[5312r,5384r:32)[5384r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 5256r 30 at 5264r 31 at 5304r 32 at 5312r 33 at 5384r
     %219 L0000000000000040:	[4544r,4704r:0)  0 at 4544r
        -->	[4544r,5256r:0)  0 at 4544r
     %219:	[4544r,5264r:0)  0 at 4544r
        -->	[4544r,5264r:0)  0 at 4544r
     %6:	[440r,5664B:0)  0 at 440r
        -->	[440r,5664B:0)  0 at 440r
handleMove 4768B -> 5252B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %6:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,4768r:29)[4768r,5288r:30)[5288r,5296r:31)[5296r,5368r:32)[5368r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 4768r 31 at 5288r 32 at 5296r 33 at 5368r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,5252r:29)[5252r,5288r:30)[5288r,5296r:31)[5296r,5368r:32)[5368r,5440r:33)[5440r,5664B:1)  0 at 1120r 1 at 5440r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 5252r 31 at 5288r 32 at 5296r 33 at 5368r
     %217 L0000000000000002:	[4528r,4768r:0)  0 at 4528r
        -->	[4528r,5252r:0)  0 at 4528r
     %217:	[4528r,4768r:0)  0 at 4528r
        -->	[4528r,5252r:0)  0 at 4528r
     %6:	[440r,5664B:0)  0 at 440r
        -->	[440r,5664B:0)  0 at 440r
handleMove 4736B -> 5256B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx0:vsrprc, %31:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,4736r:29)[4736r,5288r:30)[5288r,5296r:31)[5296r,5368r:32)[5368r,5416r:33)[5416r,5664B:1)  0 at 1136r 1 at 5416r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 4736r 31 at 5288r 32 at 5296r 33 at 5368r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,5256r:29)[5256r,5288r:30)[5288r,5296r:31)[5296r,5368r:32)[5368r,5416r:33)[5416r,5664B:1)  0 at 1136r 1 at 5416r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 5256r 31 at 5288r 32 at 5296r 33 at 5368r
     %217 L0000000000000002:	[4528r,5264r:0)  0 at 4528r
        -->	[4528r,5264r:0)  0 at 4528r
     %217:	[4528r,5264r:0)  0 at 4528r
        -->	[4528r,5264r:0)  0 at 4528r
     %31:	[464r,5664B:0)  0 at 464r
        -->	[464r,5664B:0)  0 at 464r
handleMove 4640B -> 5252B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,4640r:28)[4640r,5256r:29)[5256r,5288r:30)[5288r,5296r:31)[5296r,5368r:32)[5368r,5416r:33)[5416r,5664B:1)  0 at 1136r 1 at 5416r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 4640r 30 at 5256r 31 at 5288r 32 at 5296r 33 at 5368r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,5252r:28)[5252r,5256r:29)[5256r,5288r:30)[5288r,5296r:31)[5296r,5368r:32)[5368r,5416r:33)[5416r,5664B:1)  0 at 1136r 1 at 5416r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 5252r 30 at 5256r 31 at 5288r 32 at 5296r 33 at 5368r
     %217 L0000000000000040:	[4528r,4672r:0)  0 at 4528r
        -->	[4528r,5252r:0)  0 at 4528r
     %217:	[4528r,5264r:0)  0 at 4528r
        -->	[4528r,5264r:0)  0 at 4528r
     %31:	[464r,5664B:0)  0 at 464r
        -->	[464r,5664B:0)  0 at 464r
handleMove 4672B -> 5256B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %217.sub_vsx1:vsrprc, %197:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,4672r:28)[4672r,5280r:29)[5280r,5320r:30)[5320r,5328r:31)[5328r,5400r:32)[5400r,5448r:33)[5448r,5664B:1)  0 at 1120r 1 at 5448r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 4672r 30 at 5280r 31 at 5320r 32 at 5328r 33 at 5400r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,5256r:28)[5256r,5280r:29)[5280r,5320r:30)[5320r,5328r:31)[5328r,5400r:32)[5400r,5448r:33)[5448r,5664B:1)  0 at 1120r 1 at 5448r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 5256r 30 at 5280r 31 at 5320r 32 at 5328r 33 at 5400r
     %217 L0000000000000040:	[4528r,5264r:0)  0 at 4528r
        -->	[4528r,5264r:0)  0 at 4528r
     %217:	[4528r,5280r:0)  0 at 4528r
        -->	[4528r,5280r:0)  0 at 4528r
     %197:	[4208r,4672r:0)  0 at 4208r
        -->	[4208r,5256r:0)  0 at 4208r
handleMove 4496B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %200.sub_vsx0:vsrprc, %197:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,4496r:27)[4496r,5288r:28)[5288r,5296r:29)[5296r,5336r:30)[5336r,5344r:31)[5344r,5416r:32)[5416r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 4496r 29 at 5288r 30 at 5296r 31 at 5336r 32 at 5344r 33 at 5416r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,5252r:27)[5252r,5288r:28)[5288r,5296r:29)[5296r,5336r:30)[5336r,5344r:31)[5344r,5416r:32)[5416r,5472r:33)[5472r,5664B:1)  0 at 1104r 1 at 5472r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 5252r 29 at 5288r 30 at 5296r 31 at 5336r 32 at 5344r 33 at 5416r
     %200 L0000000000000002:	[4240r,4496r:0)  0 at 4240r
        -->	[4240r,5252r:0)  0 at 4240r
     %200:	[4240r,4496r:0)  0 at 4240r
        -->	[4240r,5252r:0)  0 at 4240r
     %197:	[4208r,5256r:0)  0 at 4208r
        -->	[4208r,5256r:0)  0 at 4208r
handleMove 4400B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %200.sub_vsx1:vsrprc, %195:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,4400r:26)[4400r,5264r:27)[5264r,5304r:28)[5304r,5312r:29)[5312r,5352r:30)[5352r,5360r:31)[5360r,5432r:32)[5432r,5480r:33)[5480r,5664B:1)  0 at 1104r 1 at 5480r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 4400r 28 at 5264r 29 at 5304r 30 at 5312r 31 at 5352r 32 at 5360r 33 at 5432r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,5256r:26)[5256r,5264r:27)[5264r,5304r:28)[5304r,5312r:29)[5312r,5352r:30)[5352r,5360r:31)[5360r,5432r:32)[5432r,5480r:33)[5480r,5664B:1)  0 at 1104r 1 at 5480r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 5256r 28 at 5264r 29 at 5304r 30 at 5312r 31 at 5352r 32 at 5360r 33 at 5432r
     %200 L0000000000000040:	[4240r,4400r:0)  0 at 4240r
        -->	[4240r,5256r:0)  0 at 4240r
     %200:	[4240r,5264r:0)  0 at 4240r
        -->	[4240r,5264r:0)  0 at 4240r
     %195:	[4192r,4464r:0)  0 at 4192r
        -->	[4192r,5256r:0)  0 at 4192r
handleMove 4464B -> 5252B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %195:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,4464r:27)[4464r,5272r:28)[5272r,5296r:29)[5296r,5336r:30)[5336r,5344r:31)[5344r,5416r:32)[5416r,5464r:33)[5464r,5664B:1)  0 at 1120r 1 at 5464r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 4464r 29 at 5272r 30 at 5296r 31 at 5336r 32 at 5344r 33 at 5416r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,5252r:27)[5252r,5272r:28)[5272r,5296r:29)[5296r,5336r:30)[5336r,5344r:31)[5344r,5416r:32)[5416r,5464r:33)[5464r,5664B:1)  0 at 1120r 1 at 5464r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 5252r 29 at 5272r 30 at 5296r 31 at 5336r 32 at 5344r 33 at 5416r
     %198 L0000000000000002:	[4224r,4464r:0)  0 at 4224r
        -->	[4224r,5252r:0)  0 at 4224r
     %198:	[4224r,4464r:0)  0 at 4224r
        -->	[4224r,5252r:0)  0 at 4224r
     %195:	[4192r,5256r:0)  0 at 4192r
        -->	[4192r,5256r:0)  0 at 4192r
handleMove 4432B -> 5256B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx0:vsrprc, %193:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,4432r:27)[4432r,5296r:28)[5296r,5304r:29)[5304r,5336r:30)[5336r,5344r:31)[5344r,5416r:32)[5416r,5464r:33)[5464r,5664B:1)  0 at 1136r 1 at 5464r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 4432r 29 at 5296r 30 at 5304r 31 at 5336r 32 at 5344r 33 at 5416r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,5256r:27)[5256r,5296r:28)[5296r,5304r:29)[5304r,5336r:30)[5336r,5344r:31)[5344r,5416r:32)[5416r,5464r:33)[5464r,5664B:1)  0 at 1136r 1 at 5464r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 5256r 29 at 5296r 30 at 5304r 31 at 5336r 32 at 5344r 33 at 5416r
     %198 L0000000000000002:	[4224r,5264r:0)  0 at 4224r
        -->	[4224r,5264r:0)  0 at 4224r
     %198:	[4224r,5264r:0)  0 at 4224r
        -->	[4224r,5264r:0)  0 at 4224r
     %193:	[4176r,4432r:0)  0 at 4176r
        -->	[4176r,5256r:0)  0 at 4176r
handleMove 4368B -> 5252B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %174:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,4368r:26)[4368r,5264r:27)[5264r,5288r:28)[5288r,5312r:29)[5312r,5352r:30)[5352r,5360r:31)[5360r,5432r:32)[5432r,5480r:33)[5480r,5664B:1)  0 at 1120r 1 at 5480r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 4368r 28 at 5264r 29 at 5288r 30 at 5312r 31 at 5352r 32 at 5360r 33 at 5432r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,5252r:26)[5252r,5264r:27)[5264r,5288r:28)[5288r,5312r:29)[5312r,5352r:30)[5352r,5360r:31)[5360r,5432r:32)[5432r,5480r:33)[5480r,5664B:1)  0 at 1120r 1 at 5480r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 5252r 28 at 5264r 29 at 5288r 30 at 5312r 31 at 5352r 32 at 5360r 33 at 5432r
     %198 L0000000000000040:	[4224r,4368r:0)  0 at 4224r
        -->	[4224r,5252r:0)  0 at 4224r
     %198:	[4224r,5264r:0)  0 at 4224r
        -->	[4224r,5264r:0)  0 at 4224r
     %174:	[3872r,4368r:0)  0 at 3872r
        -->	[3872r,5252r:0)  0 at 3872r
handleMove 4336B -> 5256B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %198.sub_vsx1:vsrprc, %172:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,4336r:26)[4336r,5272r:27)[5272r,5312r:28)[5312r,5320r:29)[5320r,5352r:30)[5352r,5360r:31)[5360r,5432r:32)[5432r,5480r:33)[5480r,5664B:1)  0 at 1136r 1 at 5480r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 4336r 28 at 5272r 29 at 5312r 30 at 5320r 31 at 5352r 32 at 5360r 33 at 5432r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,5256r:26)[5256r,5272r:27)[5272r,5312r:28)[5312r,5320r:29)[5320r,5352r:30)[5352r,5360r:31)[5360r,5432r:32)[5432r,5480r:33)[5480r,5664B:1)  0 at 1136r 1 at 5480r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 5256r 28 at 5272r 29 at 5312r 30 at 5320r 31 at 5352r 32 at 5360r 33 at 5432r
     %198 L0000000000000040:	[4224r,5264r:0)  0 at 4224r
        -->	[4224r,5264r:0)  0 at 4224r
     %198:	[4224r,5280r:0)  0 at 4224r
        -->	[4224r,5280r:0)  0 at 4224r
     %172:	[3856r,4336r:0)  0 at 3856r
        -->	[3856r,5256r:0)  0 at 3856r
handleMove 4160B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %177.sub_vsx0:vsrprc, %174:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,4160r:25)[4160r,5288r:26)[5288r,5296r:27)[5296r,5336r:28)[5336r,5344r:29)[5344r,5384r:30)[5384r,5392r:31)[5392r,5464r:32)[5464r,5512r:33)[5512r,5664B:1)  0 at 1104r 1 at 5512r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 4160r 27 at 5288r 28 at 5296r 29 at 5336r 30 at 5344r 31 at 5384r 32 at 5392r 33 at 5464r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,5252r:25)[5252r,5288r:26)[5288r,5296r:27)[5296r,5336r:28)[5336r,5344r:29)[5344r,5384r:30)[5384r,5392r:31)[5392r,5464r:32)[5464r,5512r:33)[5512r,5664B:1)  0 at 1104r 1 at 5512r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 5252r 27 at 5288r 28 at 5296r 29 at 5336r 30 at 5344r 31 at 5384r 32 at 5392r 33 at 5464r
     %177 L0000000000000002:	[3904r,4160r:0)  0 at 3904r
        -->	[3904r,5252r:0)  0 at 3904r
     %177:	[3904r,4160r:0)  0 at 3904r
        -->	[3904r,5252r:0)  0 at 3904r
     %174:	[3872r,5264r:0)  0 at 3872r
        -->	[3872r,5264r:0)  0 at 3872r
handleMove 4064B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %177.sub_vsx1:vsrprc, %170:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,4064r:24)[4064r,5264r:25)[5264r,5304r:26)[5304r,5312r:27)[5312r,5352r:28)[5352r,5360r:29)[5360r,5400r:30)[5400r,5408r:31)[5408r,5480r:32)[5480r,5528r:33)[5528r,5664B:1)  0 at 1104r 1 at 5528r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 4064r 26 at 5264r 27 at 5304r 28 at 5312r 29 at 5352r 30 at 5360r 31 at 5400r 32 at 5408r 33 at 5480r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,5256r:24)[5256r,5264r:25)[5264r,5304r:26)[5304r,5312r:27)[5312r,5352r:28)[5352r,5360r:29)[5360r,5400r:30)[5400r,5408r:31)[5408r,5480r:32)[5480r,5528r:33)[5528r,5664B:1)  0 at 1104r 1 at 5528r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 5256r 26 at 5264r 27 at 5304r 28 at 5312r 29 at 5352r 30 at 5360r 31 at 5400r 32 at 5408r 33 at 5480r
     %177 L0000000000000040:	[3904r,4064r:0)  0 at 3904r
        -->	[3904r,5256r:0)  0 at 3904r
     %177:	[3904r,5264r:0)  0 at 3904r
        -->	[3904r,5264r:0)  0 at 3904r
     %170:	[3840r,4128r:0)  0 at 3840r
        -->	[3840r,5256r:0)  0 at 3840r
handleMove 4128B -> 5252B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %170:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,4128r:25)[4128r,5280r:26)[5280r,5296r:27)[5296r,5320r:28)[5320r,5344r:29)[5344r,5384r:30)[5384r,5392r:31)[5392r,5464r:32)[5464r,5512r:33)[5512r,5664B:1)  0 at 1120r 1 at 5512r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 4128r 27 at 5280r 28 at 5296r 29 at 5320r 30 at 5344r 31 at 5384r 32 at 5392r 33 at 5464r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,5252r:25)[5252r,5280r:26)[5280r,5296r:27)[5296r,5320r:28)[5320r,5344r:29)[5344r,5384r:30)[5384r,5392r:31)[5392r,5464r:32)[5464r,5512r:33)[5512r,5664B:1)  0 at 1120r 1 at 5512r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 5252r 27 at 5280r 28 at 5296r 29 at 5320r 30 at 5344r 31 at 5384r 32 at 5392r 33 at 5464r
     %175 L0000000000000002:	[3888r,4128r:0)  0 at 3888r
        -->	[3888r,5252r:0)  0 at 3888r
     %175:	[3888r,4128r:0)  0 at 3888r
        -->	[3888r,5252r:0)  0 at 3888r
     %170:	[3840r,5256r:0)  0 at 3840r
        -->	[3840r,5256r:0)  0 at 3840r
handleMove 4096B -> 5256B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx0:vsrprc, %168:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,4096r:25)[4096r,5288r:26)[5288r,5304r:27)[5304r,5344r:28)[5344r,5352r:29)[5352r,5384r:30)[5384r,5392r:31)[5392r,5464r:32)[5464r,5512r:33)[5512r,5664B:1)  0 at 1136r 1 at 5512r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 4096r 27 at 5288r 28 at 5304r 29 at 5344r 30 at 5352r 31 at 5384r 32 at 5392r 33 at 5464r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,5256r:25)[5256r,5288r:26)[5288r,5304r:27)[5304r,5344r:28)[5344r,5352r:29)[5352r,5384r:30)[5384r,5392r:31)[5392r,5464r:32)[5464r,5512r:33)[5512r,5664B:1)  0 at 1136r 1 at 5512r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 5256r 27 at 5288r 28 at 5304r 29 at 5344r 30 at 5352r 31 at 5384r 32 at 5392r 33 at 5464r
     %175 L0000000000000002:	[3888r,5264r:0)  0 at 3888r
        -->	[3888r,5264r:0)  0 at 3888r
     %175:	[3888r,5264r:0)  0 at 3888r
        -->	[3888r,5264r:0)  0 at 3888r
     %168:	[3824r,4096r:0)  0 at 3824r
        -->	[3824r,5256r:0)  0 at 3824r
handleMove 4032B -> 5252B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %149:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,4032r:24)[4032r,5264r:25)[5264r,5296r:26)[5296r,5312r:27)[5312r,5336r:28)[5336r,5360r:29)[5360r,5400r:30)[5400r,5408r:31)[5408r,5480r:32)[5480r,5528r:33)[5528r,5664B:1)  0 at 1120r 1 at 5528r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 4032r 26 at 5264r 27 at 5296r 28 at 5312r 29 at 5336r 30 at 5360r 31 at 5400r 32 at 5408r 33 at 5480r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,5252r:24)[5252r,5264r:25)[5264r,5296r:26)[5296r,5312r:27)[5312r,5336r:28)[5336r,5360r:29)[5360r,5400r:30)[5400r,5408r:31)[5408r,5480r:32)[5480r,5528r:33)[5528r,5664B:1)  0 at 1120r 1 at 5528r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 5252r 26 at 5264r 27 at 5296r 28 at 5312r 29 at 5336r 30 at 5360r 31 at 5400r 32 at 5408r 33 at 5480r
     %175 L0000000000000040:	[3888r,4032r:0)  0 at 3888r
        -->	[3888r,5252r:0)  0 at 3888r
     %175:	[3888r,5264r:0)  0 at 3888r
        -->	[3888r,5264r:0)  0 at 3888r
     %149:	[3520r,4032r:0)  0 at 3520r
        -->	[3520r,5252r:0)  0 at 3520r
handleMove 4000B -> 5256B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %175.sub_vsx1:vsrprc, %147:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,4000r:24)[4000r,5272r:25)[5272r,5304r:26)[5304r,5320r:27)[5320r,5360r:28)[5360r,5368r:29)[5368r,5400r:30)[5400r,5408r:31)[5408r,5480r:32)[5480r,5528r:33)[5528r,5664B:1)  0 at 1136r 1 at 5528r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 4000r 26 at 5272r 27 at 5304r 28 at 5320r 29 at 5360r 30 at 5368r 31 at 5400r 32 at 5408r 33 at 5480r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,5256r:24)[5256r,5272r:25)[5272r,5304r:26)[5304r,5320r:27)[5320r,5360r:28)[5360r,5368r:29)[5368r,5400r:30)[5400r,5408r:31)[5408r,5480r:32)[5480r,5528r:33)[5528r,5664B:1)  0 at 1136r 1 at 5528r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 5256r 26 at 5272r 27 at 5304r 28 at 5320r 29 at 5360r 30 at 5368r 31 at 5400r 32 at 5408r 33 at 5480r
     %175 L0000000000000040:	[3888r,5264r:0)  0 at 3888r
        -->	[3888r,5264r:0)  0 at 3888r
     %175:	[3888r,5280r:0)  0 at 3888r
        -->	[3888r,5280r:0)  0 at 3888r
     %147:	[3504r,4000r:0)  0 at 3504r
        -->	[3504r,5256r:0)  0 at 3504r
handleMove 3808B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %152.sub_vsx0:vsrprc, %149:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,3808r:23)[3808r,5288r:24)[5288r,5296r:25)[5296r,5336r:26)[5336r,5344r:27)[5344r,5384r:28)[5384r,5392r:29)[5392r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5664B:1)  0 at 1104r 1 at 5560r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 3808r 25 at 5288r 26 at 5296r 27 at 5336r 28 at 5344r 29 at 5384r 30 at 5392r 31 at 5432r 32 at 5440r 33 at 5512r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,5252r:23)[5252r,5288r:24)[5288r,5296r:25)[5296r,5336r:26)[5336r,5344r:27)[5344r,5384r:28)[5384r,5392r:29)[5392r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5664B:1)  0 at 1104r 1 at 5560r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 5252r 25 at 5288r 26 at 5296r 27 at 5336r 28 at 5344r 29 at 5384r 30 at 5392r 31 at 5432r 32 at 5440r 33 at 5512r
     %152 L0000000000000002:	[3552r,3808r:0)  0 at 3552r
        -->	[3552r,5252r:0)  0 at 3552r
     %152:	[3552r,3808r:0)  0 at 3552r
        -->	[3552r,5252r:0)  0 at 3552r
     %149:	[3520r,5264r:0)  0 at 3520r
        -->	[3520r,5264r:0)  0 at 3520r
handleMove 3712B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %152.sub_vsx1:vsrprc, %145:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,3712r:22)[3712r,5264r:23)[5264r,5304r:24)[5304r,5312r:25)[5312r,5352r:26)[5352r,5360r:27)[5360r,5400r:28)[5400r,5408r:29)[5408r,5448r:30)[5448r,5456r:31)[5456r,5528r:32)[5528r,5576r:33)[5576r,5672B:1)  0 at 1104r 1 at 5576r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 3712r 24 at 5264r 25 at 5304r 26 at 5312r 27 at 5352r 28 at 5360r 29 at 5400r 30 at 5408r 31 at 5448r 32 at 5456r 33 at 5528r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,5256r:22)[5256r,5264r:23)[5264r,5304r:24)[5304r,5312r:25)[5312r,5352r:26)[5352r,5360r:27)[5360r,5400r:28)[5400r,5408r:29)[5408r,5448r:30)[5448r,5456r:31)[5456r,5528r:32)[5528r,5576r:33)[5576r,5672B:1)  0 at 1104r 1 at 5576r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 5256r 24 at 5264r 25 at 5304r 26 at 5312r 27 at 5352r 28 at 5360r 29 at 5400r 30 at 5408r 31 at 5448r 32 at 5456r 33 at 5528r
     %152 L0000000000000040:	[3552r,3712r:0)  0 at 3552r
        -->	[3552r,5256r:0)  0 at 3552r
     %152:	[3552r,5264r:0)  0 at 3552r
        -->	[3552r,5264r:0)  0 at 3552r
     %145:	[3488r,3776r:0)  0 at 3488r
        -->	[3488r,5256r:0)  0 at 3488r
handleMove 3776B -> 5252B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %145:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,3776r:23)[3776r,5280r:24)[5280r,5296r:25)[5296r,5328r:26)[5328r,5344r:27)[5344r,5368r:28)[5368r,5392r:29)[5392r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5672B:1)  0 at 1120r 1 at 5560r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 3776r 25 at 5280r 26 at 5296r 27 at 5328r 28 at 5344r 29 at 5368r 30 at 5392r 31 at 5432r 32 at 5440r 33 at 5512r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,5252r:23)[5252r,5280r:24)[5280r,5296r:25)[5296r,5328r:26)[5328r,5344r:27)[5344r,5368r:28)[5368r,5392r:29)[5392r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5672B:1)  0 at 1120r 1 at 5560r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 5252r 25 at 5280r 26 at 5296r 27 at 5328r 28 at 5344r 29 at 5368r 30 at 5392r 31 at 5432r 32 at 5440r 33 at 5512r
     %150 L0000000000000002:	[3536r,3776r:0)  0 at 3536r
        -->	[3536r,5252r:0)  0 at 3536r
     %150:	[3536r,3776r:0)  0 at 3536r
        -->	[3536r,5252r:0)  0 at 3536r
     %145:	[3488r,5256r:0)  0 at 3488r
        -->	[3488r,5256r:0)  0 at 3488r
handleMove 3744B -> 5256B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx0:vsrprc, %143:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,3744r:23)[3744r,5288r:24)[5288r,5304r:25)[5304r,5336r:26)[5336r,5352r:27)[5352r,5392r:28)[5392r,5400r:29)[5400r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5688B:1)  0 at 1136r 1 at 5560r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 3744r 25 at 5288r 26 at 5304r 27 at 5336r 28 at 5352r 29 at 5392r 30 at 5400r 31 at 5432r 32 at 5440r 33 at 5512r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,5256r:23)[5256r,5288r:24)[5288r,5304r:25)[5304r,5336r:26)[5336r,5352r:27)[5352r,5392r:28)[5392r,5400r:29)[5400r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5688B:1)  0 at 1136r 1 at 5560r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 5256r 25 at 5288r 26 at 5304r 27 at 5336r 28 at 5352r 29 at 5392r 30 at 5400r 31 at 5432r 32 at 5440r 33 at 5512r
     %150 L0000000000000002:	[3536r,5264r:0)  0 at 3536r
        -->	[3536r,5264r:0)  0 at 3536r
     %150:	[3536r,5264r:0)  0 at 3536r
        -->	[3536r,5264r:0)  0 at 3536r
     %143:	[3472r,3744r:0)  0 at 3472r
        -->	[3472r,5256r:0)  0 at 3472r
handleMove 3648B -> 5252B: %290:vsrc = contract nofpexcept XVMADDADP %290:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %31:vsrc, implicit $rm
     %290:	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,3648r:22)[3648r,5256r:23)[5256r,5288r:24)[5288r,5304r:25)[5304r,5336r:26)[5336r,5352r:27)[5352r,5392r:28)[5392r,5400r:29)[5400r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5688B:1)  0 at 1136r 1 at 5560r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 3648r 24 at 5256r 25 at 5288r 26 at 5304r 27 at 5336r 28 at 5352r 29 at 5392r 30 at 5400r 31 at 5432r 32 at 5440r 33 at 5512r
        -->	[1136r,1192B:0)[1192B,1328r:2)[1328r,1424r:3)[1424r,1600r:4)[1600r,1696r:5)[1696r,1792r:6)[1792r,1888r:7)[1888r,1984r:8)[1984r,2080r:9)[2080r,2192r:10)[2192r,2288r:11)[2288r,2384r:12)[2384r,2480r:13)[2480r,2576r:14)[2576r,2672r:15)[2672r,2784r:16)[2784r,2880r:17)[2880r,2992r:18)[2992r,3088r:19)[3088r,3296r:20)[3296r,3392r:21)[3392r,5252r:22)[5252r,5256r:23)[5256r,5288r:24)[5288r,5304r:25)[5304r,5336r:26)[5336r,5352r:27)[5352r,5392r:28)[5392r,5400r:29)[5400r,5432r:30)[5432r,5440r:31)[5440r,5512r:32)[5512r,5560r:33)[5560r,5688B:1)  0 at 1136r 1 at 5560r 2 at 1192B-phi 3 at 1328r 4 at 1424r 5 at 1600r 6 at 1696r 7 at 1792r 8 at 1888r 9 at 1984r 10 at 2080r 11 at 2192r 12 at 2288r 13 at 2384r 14 at 2480r 15 at 2576r 16 at 2672r 17 at 2784r 18 at 2880r 19 at 2992r 20 at 3088r 21 at 3296r 22 at 3392r 23 at 5252r 24 at 5256r 25 at 5288r 26 at 5304r 27 at 5336r 28 at 5352r 29 at 5392r 30 at 5400r 31 at 5432r 32 at 5440r 33 at 5512r
     %150 L0000000000000040:	[3536r,3680r:0)  0 at 3536r
        -->	[3536r,5252r:0)  0 at 3536r
     %150:	[3536r,5264r:0)  0 at 3536r
        -->	[3536r,5264r:0)  0 at 3536r
     %31:	[464r,5688B:0)  0 at 464r
        -->	[464r,5688B:0)  0 at 464r
handleMove 3680B -> 5256B: %289:vsrc = contract nofpexcept XVMADDADP %289:vsrc(tied-def 0), %150.sub_vsx1:vsrprc, %124:vsrc, implicit $rm
     %289:	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,3680r:22)[3680r,5280r:23)[5280r,5312r:24)[5312r,5328r:25)[5328r,5360r:26)[5360r,5376r:27)[5376r,5400r:28)[5400r,5424r:29)[5424r,5464r:30)[5464r,5472r:31)[5472r,5544r:32)[5544r,5592r:33)[5592r,5704B:1)  0 at 1120r 1 at 5592r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 3680r 24 at 5280r 25 at 5312r 26 at 5328r 27 at 5360r 28 at 5376r 29 at 5400r 30 at 5424r 31 at 5464r 32 at 5472r 33 at 5544r
        -->	[1120r,1192B:0)[1192B,1360r:2)[1360r,1456r:3)[1456r,1632r:4)[1632r,1728r:5)[1728r,1824r:6)[1824r,1920r:7)[1920r,2016r:8)[2016r,2112r:9)[2112r,2224r:10)[2224r,2320r:11)[2320r,2416r:12)[2416r,2512r:13)[2512r,2608r:14)[2608r,2704r:15)[2704r,2816r:16)[2816r,2912r:17)[2912r,3024r:18)[3024r,3120r:19)[3120r,3328r:20)[3328r,3424r:21)[3424r,5256r:22)[5256r,5280r:23)[5280r,5312r:24)[5312r,5328r:25)[5328r,5360r:26)[5360r,5376r:27)[5376r,5400r:28)[5400r,5424r:29)[5424r,5464r:30)[5464r,5472r:31)[5472r,5544r:32)[5544r,5592r:33)[5592r,5704B:1)  0 at 1120r 1 at 5592r 2 at 1192B-phi 3 at 1360r 4 at 1456r 5 at 1632r 6 at 1728r 7 at 1824r 8 at 1920r 9 at 2016r 10 at 2112r 11 at 2224r 12 at 2320r 13 at 2416r 14 at 2512r 15 at 2608r 16 at 2704r 17 at 2816r 18 at 2912r 19 at 3024r 20 at 3120r 21 at 3328r 22 at 3424r 23 at 5256r 24 at 5280r 25 at 5312r 26 at 5328r 27 at 5360r 28 at 5376r 29 at 5400r 30 at 5424r 31 at 5464r 32 at 5472r 33 at 5544r
     %150 L0000000000000040:	[3536r,5264r:0)  0 at 3536r
        -->	[3536r,5264r:0)  0 at 3536r
     %150:	[3536r,5280r:0)  0 at 3536r
        -->	[3536r,5280r:0)  0 at 3536r
     %124:	[3168r,3680r:0)  0 at 3168r
        -->	[3168r,5256r:0)  0 at 3168r
handleMove 3456B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %127.sub_vsx0:vsrprc, %124:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,3456r:21)[3456r,5288r:22)[5288r,5296r:23)[5296r,5336r:24)[5336r,5344r:25)[5344r,5384r:26)[5384r,5392r:27)[5392r,5432r:28)[5432r,5440r:29)[5440r,5480r:30)[5480r,5488r:31)[5488r,5560r:32)[5560r,5608r:33)[5608r,5704B:1)  0 at 1104r 1 at 5608r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 3456r 23 at 5288r 24 at 5296r 25 at 5336r 26 at 5344r 27 at 5384r 28 at 5392r 29 at 5432r 30 at 5440r 31 at 5480r 32 at 5488r 33 at 5560r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,5252r:21)[5252r,5288r:22)[5288r,5296r:23)[5296r,5336r:24)[5336r,5344r:25)[5344r,5384r:26)[5384r,5392r:27)[5392r,5432r:28)[5432r,5440r:29)[5440r,5480r:30)[5480r,5488r:31)[5488r,5560r:32)[5560r,5608r:33)[5608r,5704B:1)  0 at 1104r 1 at 5608r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 5252r 23 at 5288r 24 at 5296r 25 at 5336r 26 at 5344r 27 at 5384r 28 at 5392r 29 at 5432r 30 at 5440r 31 at 5480r 32 at 5488r 33 at 5560r
     %127 L0000000000000002:	[3200r,3456r:0)  0 at 3200r
        -->	[3200r,5252r:0)  0 at 3200r
     %127:	[3200r,3456r:0)  0 at 3200r
        -->	[3200r,5252r:0)  0 at 3200r
     %124:	[3168r,5256r:0)  0 at 3168r
        -->	[3168r,5256r:0)  0 at 3168r
handleMove 3360B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %127.sub_vsx1:vsrprc, %5:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,3360r:20)[3360r,5264r:21)[5264r,5304r:22)[5304r,5312r:23)[5312r,5352r:24)[5352r,5360r:25)[5360r,5400r:26)[5400r,5408r:27)[5408r,5448r:28)[5448r,5456r:29)[5456r,5496r:30)[5496r,5504r:31)[5504r,5576r:32)[5576r,5624r:33)[5624r,5720B:1)  0 at 1104r 1 at 5624r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 3360r 22 at 5264r 23 at 5304r 24 at 5312r 25 at 5352r 26 at 5360r 27 at 5400r 28 at 5408r 29 at 5448r 30 at 5456r 31 at 5496r 32 at 5504r 33 at 5576r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,5256r:20)[5256r,5264r:21)[5264r,5304r:22)[5304r,5312r:23)[5312r,5352r:24)[5352r,5360r:25)[5360r,5400r:26)[5400r,5408r:27)[5408r,5448r:28)[5448r,5456r:29)[5456r,5496r:30)[5496r,5504r:31)[5504r,5576r:32)[5576r,5624r:33)[5624r,5720B:1)  0 at 1104r 1 at 5624r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 5256r 22 at 5264r 23 at 5304r 24 at 5312r 25 at 5352r 26 at 5360r 27 at 5400r 28 at 5408r 29 at 5448r 30 at 5456r 31 at 5496r 32 at 5504r 33 at 5576r
     %127 L0000000000000040:	[3200r,3360r:0)  0 at 3200r
        -->	[3200r,5256r:0)  0 at 3200r
     %127:	[3200r,5264r:0)  0 at 3200r
        -->	[3200r,5264r:0)  0 at 3200r
     %5:	[436r,5720B:0)  0 at 436r
        -->	[436r,5720B:0)  0 at 436r
handleMove 3152B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,3152r:19)[3152r,5256r:20)[5256r,5264r:21)[5264r,5304r:22)[5304r,5312r:23)[5312r,5352r:24)[5352r,5360r:25)[5360r,5400r:26)[5400r,5408r:27)[5408r,5448r:28)[5448r,5456r:29)[5456r,5496r:30)[5496r,5504r:31)[5504r,5576r:32)[5576r,5624r:33)[5624r,5720B:1)  0 at 1104r 1 at 5624r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 3152r 21 at 5256r 22 at 5264r 23 at 5304r 24 at 5312r 25 at 5352r 26 at 5360r 27 at 5400r 28 at 5408r 29 at 5448r 30 at 5456r 31 at 5496r 32 at 5504r 33 at 5576r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,5252r:19)[5252r,5256r:20)[5256r,5264r:21)[5264r,5304r:22)[5304r,5312r:23)[5312r,5352r:24)[5352r,5360r:25)[5360r,5400r:26)[5400r,5408r:27)[5408r,5448r:28)[5448r,5456r:29)[5456r,5496r:30)[5496r,5504r:31)[5504r,5576r:32)[5576r,5624r:33)[5624r,5720B:1)  0 at 1104r 1 at 5624r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 5252r 21 at 5256r 22 at 5264r 23 at 5304r 24 at 5312r 25 at 5352r 26 at 5360r 27 at 5400r 28 at 5408r 29 at 5448r 30 at 5456r 31 at 5496r 32 at 5504r 33 at 5576r
     %31:	[464r,5720B:0)  0 at 464r
        -->	[464r,5720B:0)  0 at 464r
handleMove 3056B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,3056r:18)[3056r,5264r:19)[5264r,5272r:20)[5272r,5280r:21)[5280r,5320r:22)[5320r,5328r:23)[5328r,5368r:24)[5368r,5376r:25)[5376r,5416r:26)[5416r,5424r:27)[5424r,5464r:28)[5464r,5472r:29)[5472r,5512r:30)[5512r,5520r:31)[5520r,5592r:32)[5592r,5640r:33)[5640r,5736B:1)  0 at 1104r 1 at 5640r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 3056r 20 at 5264r 21 at 5272r 22 at 5280r 23 at 5320r 24 at 5328r 25 at 5368r 26 at 5376r 27 at 5416r 28 at 5424r 29 at 5464r 30 at 5472r 31 at 5512r 32 at 5520r 33 at 5592r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,5256r:18)[5256r,5264r:19)[5264r,5272r:20)[5272r,5280r:21)[5280r,5320r:22)[5320r,5328r:23)[5328r,5368r:24)[5368r,5376r:25)[5376r,5416r:26)[5416r,5424r:27)[5424r,5464r:28)[5464r,5472r:29)[5472r,5512r:30)[5512r,5520r:31)[5520r,5592r:32)[5592r,5640r:33)[5640r,5736B:1)  0 at 1104r 1 at 5640r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 5256r 20 at 5264r 21 at 5272r 22 at 5280r 23 at 5320r 24 at 5328r 25 at 5368r 26 at 5376r 27 at 5416r 28 at 5424r 29 at 5464r 30 at 5472r 31 at 5512r 32 at 5520r 33 at 5592r
     %31:	[464r,5736B:0)  0 at 464r
        -->	[464r,5736B:0)  0 at 464r
handleMove 2944B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,2944r:17)[2944r,5256r:18)[5256r,5264r:19)[5264r,5272r:20)[5272r,5280r:21)[5280r,5320r:22)[5320r,5328r:23)[5328r,5368r:24)[5368r,5376r:25)[5376r,5416r:26)[5416r,5424r:27)[5424r,5464r:28)[5464r,5472r:29)[5472r,5512r:30)[5512r,5520r:31)[5520r,5592r:32)[5592r,5640r:33)[5640r,5736B:1)  0 at 1104r 1 at 5640r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 2944r 19 at 5256r 20 at 5264r 21 at 5272r 22 at 5280r 23 at 5320r 24 at 5328r 25 at 5368r 26 at 5376r 27 at 5416r 28 at 5424r 29 at 5464r 30 at 5472r 31 at 5512r 32 at 5520r 33 at 5592r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,5252r:17)[5252r,5256r:18)[5256r,5264r:19)[5264r,5272r:20)[5272r,5280r:21)[5280r,5320r:22)[5320r,5328r:23)[5328r,5368r:24)[5368r,5376r:25)[5376r,5416r:26)[5416r,5424r:27)[5424r,5464r:28)[5464r,5472r:29)[5472r,5512r:30)[5512r,5520r:31)[5520r,5592r:32)[5592r,5640r:33)[5640r,5736B:1)  0 at 1104r 1 at 5640r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 5252r 19 at 5256r 20 at 5264r 21 at 5272r 22 at 5280r 23 at 5320r 24 at 5328r 25 at 5368r 26 at 5376r 27 at 5416r 28 at 5424r 29 at 5464r 30 at 5472r 31 at 5512r 32 at 5520r 33 at 5592r
     %31:	[464r,5736B:0)  0 at 464r
        -->	[464r,5736B:0)  0 at 464r
handleMove 2848B -> 5256B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %108:vsrc, %31:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,2848r:16)[2848r,5264r:17)[5264r,5272r:18)[5272r,5280r:19)[5280r,5288r:20)[5288r,5296r:21)[5296r,5336r:22)[5336r,5344r:23)[5344r,5384r:24)[5384r,5392r:25)[5392r,5432r:26)[5432r,5440r:27)[5440r,5480r:28)[5480r,5488r:29)[5488r,5528r:30)[5528r,5536r:31)[5536r,5608r:32)[5608r,5656r:33)[5656r,5752B:1)  0 at 1104r 1 at 5656r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 2848r 18 at 5264r 19 at 5272r 20 at 5280r 21 at 5288r 22 at 5296r 23 at 5336r 24 at 5344r 25 at 5384r 26 at 5392r 27 at 5432r 28 at 5440r 29 at 5480r 30 at 5488r 31 at 5528r 32 at 5536r 33 at 5608r
        -->	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,5256r:16)[5256r,5264r:17)[5264r,5272r:18)[5272r,5280r:19)[5280r,5288r:20)[5288r,5296r:21)[5296r,5336r:22)[5336r,5344r:23)[5344r,5384r:24)[5384r,5392r:25)[5392r,5432r:26)[5432r,5440r:27)[5440r,5480r:28)[5480r,5488r:29)[5488r,5528r:30)[5528r,5536r:31)[5536r,5608r:32)[5608r,5656r:33)[5656r,5752B:1)  0 at 1104r 1 at 5656r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r 15 at 2640r 16 at 2736r 17 at 5256r 18 at 5264r 19 at 5272r 20 at 5280r 21 at 5288r 22 at 5296r 23 at 5336r 24 at 5344r 25 at 5384r 26 at 5392r 27 at 5432r 28 at 5440r 29 at 5480r 30 at 5488r 31 at 5528r 32 at 5536r 33 at 5608r
     %108:	[2752r,2912r:0)  0 at 2752r
        -->	[2752r,5256r:0)  0 at 2752r
     %31:	[464r,5752B:0)  0 at 464r
        -->	[464r,5752B:0)  0 at 464r
handleMove 2736B -> 5252B: %288:vsrc = contract nofpexcept XVMADDADP %288:vsrc(tied-def 0), %31:vsrc, %31:vsrc, implicit $rm
     %288:	[1104r,1192B:0)[1192B,1392r:2)[1392r,1488r:3)[1488r,1664r:4)[1664r,1760r:5)[1760r,1856r:6)[1856r,1952r:7)[1952r,2048r:8)[2048r,2144r:9)[2144r,2256r:10)[2256r,2352r:11)[2352r,2448r:12)[2448r,2544r:13)[2544r,2640r:14)[2640r,2736r:15)[2736r,5256r:16)[5256r,5264r:17)[5264r,5272r:18)[5272r,5280r:19)[5280r,5288r:20)[5288r,5296r:21)[5296r,5336r:22)[5336r,5344r:23)[5344r,5384r:24)[5384r,5392r:25)[5392r,5432r:26)[5432r,5440r:27)[5440r,5480r:28)[5480r,5488r:29)[5488r,5528r:30)[5528r,5536r:31)[5536r,5608r:32)[5608r,5656r:33)[5656r,5752B:1)  0 at 1104r 1 at 5656r 2 at 1192B-phi 3 at 1392r 4 at 1488r 5 at 1664r 6 at 1760r 7 at 1856r 8 at 1952r 9 at 2048r 10 at 2144r 11 at 2256r 12 at 2352r 13 at 2448r 14 at 2544r