[llvm-dev] Lack of support for certain operations in SystemZ LLVM backend

[Kun Lu via llvm-dev]

Hi,

Recently we're running test suite of TensorFlow v2.5.0 on s390x (Ubuntu
18.04).

Test case //tensorflow/compiler/tests:sort_ops_test_cpu fails due to the
following error:

LLVM ERROR: Cannot select: 0x3ff14167ca0: f32 = fp16_to_fp 0x3ff14167f10
  0x3ff14167f10: i32,ch = load<(dereferenceable load 2 from
%ir.4, !alias.scope !6, !noalias !4), zext from i16> 0x3ff14197548,
0x3ff141678f8, undef:i64
    0x3ff141678f8: i64,ch = load<(load 8 from %ir.3)> 0x3ff14197548,
0x3ff14167890, undef:i64
      0x3ff14167890: i64 = add nuw 0x3ff141674e8, Constant:i64<8>
        0x3ff141674e8: i64,ch = CopyFromReg 0x3ff14197548, Register:i64 %2
          0x3ff14167480: i64 = Register %2
        0x3ff14167828: i64 = Constant<8>
      0x3ff14167758: i64 = undef
    0x3ff14167758: i64 = undef
In function: compare_lt_WCTTAtafbb4__.7

Other test cases such as //tensorflow/python/keras/optimizer_v2:adam_test
and //tensorflow/core/kernels/mlir_generated:abs_cpu_f16_f16_gen_test also
fail on s390x due to similar reasons. A related issue (
https://github.com/tensorflow/tensorflow/issues/44362) has been raised in
TensorFlow GitHub issues.

We think the root cause is lack of support for operations such as
FP16_TO_FP and FP_TO_FP16 which perform promotions and truncation for
half-precision (16 bit) floating numbers in the SystemZ LLVM backend
(llvm/lib/Target/SystemZ/SystemZISelLowering.cpp). Could these features be
considered to add to SystemZ LLVM backend? Thanks!

Regards,
Kun
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