[llvm-dev] [WebAssembly] Lower type in new DAG node

[Paulo Matos via llvm-dev]

David Chisnall via llvm-dev writes:

> Hi Paulo,
>
> In the CHERI port of LLVM, we have added a bunch of fat pointer MVT 
> types (iFATPTR64, iFATPTR128, and so on) and lower CHERI capabilities 
> (which, in the IR, we represent as pointers with address space 200) to 
> them in the relevant back ends (MIPS / RISC-V / AArch64).  We also add 
> explicit PTRADD DAG nodes for pointer arithmetic (GEP lowering)
>
> We can load and store an iFATPTR{width} via a normal load and store, 
> just as we can any other type.
>
> Would this address your use case?

Hi David,

I think this is quite similar to the lowering I want to perform. I will
dig deeper into the CHERI port and try to understand how that is done.

Thanks for the reference.

-- 
Paulo Matos