[llvm-dev] [X86] Is it possible to implicitly promote a virtual subregister to a super?

[Constable, Scott D via llvm-dev]

Hi All,

Suppose I have in X86 MIR SSA:

Register WideReg = MRI->createVirtualRegister(&X86::GR32RegClass);
Register NarrowReg = MRI->createVirtualRegister(&X86::GR16RegClass);
// Generate other instructions that def WideReg and NarrowReg
BuildMI(MBB, InsertPt, Loc, TII->get(CMP32rr), WideReg).addReg(NarrowReg);

The above will not pass with --verify-machineinstrs and the CMP32rr will print to something like:

// other instructions that def %ax and %ebx
cmpl %ax, %ebx

Is it possible to implicitly "promote" (for lack of a better word) the 16-bit GPR into its 32-bit super? The output should look like:

// other instructions that def %ax and %ebx
cmpl %eax, %ebx

Thanks in advance,

Scott Constable
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