[llvm-dev] How do I prevent DAGCombiner from combining ZExt/SExt(load) into LoadZExt?

[Tim Northover via llvm-dev]

On Thu, 7 Jan 2021 at 10:10, Zhang <admin at mayuyu.io> wrote:
> Combining: t5: i32 = zero_extend t4
> Creating new node: t9: i32,ch = load<(dereferenceable load 1 from %ir.2), zext from i1> t0, FrameIndex:i64<0>, undef:i64

Ah, I didn't notice it was i1, that's special because the smallest
load you have is probably actually an i8. I think most systems define
this problem away by saying that an i1 in memory occupies an entire
byte and must be either 0x00 or 0x01. Then a normal load from that
byte *is* a zext load.

For a sextload, I think LLVM converts that to an anyext load (also
implementable by your normal load instruction) followed by a separate
extension operation. At least that's what happens on AArch64.

If that doesn't work for you for some reason, you'll probably just
have to live with zextload from i1 being produced anyway and emit
multiple instructions to implement it.

Cheers.

Tim.