[llvm-dev] RFC: Allowing scalable vectors in structs to support multiple return values from intrinsics
Craig Topper via llvm-dev
llvm-dev at lists.llvm.org
Wed Jan 6 14:27:08 PST 2021
RISCV vector intrinsics have a need to return multiple scalable vector
values. We plan to use this to return multiple results from segment load
intrinsics. These instructions conceptually load multiple separate
registers. I believe SVE has similar load intrinsics, but they use wide
scalable vectors that get split during type legalization. We are struggling
to do the same since we already use the size of the fixed part of a
scalable vector to determine LMUL size. This means we have legal scalable
vector types with different fixed part sizes. This makes it very difficult
for type legalization to split a wide vector type for a segment load into
the correct number of pieces. We feel that returning multiple results and
avoiding the type legalizer is an easier path.
Unfortunately, supporting multiple scalable vectors being returned from an
intrinsic requires scalable vectors to be allowed in structs. We would
disallow such structs to be used by loads/stores/allocas/geps which would
avoid needing to determine the offsets of any of the fields in the struct.
I've posted an initial patch for the IR and verifier portions of this here
We would appreciate any feedback on this direction.
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