[llvm-dev] Problem in AMDGPU TableGen files

[Craig Topper via llvm-dev]

Are you also failing on RISCV, I see things that should fail.

For example, RISCVInstrInfoVSDPatterns.td contains

defm "" : VPatUSLoadStoreSDNodes<AddrFI>;

  Where AddrFI is a complex pattern, but VPatUSLoadStoreSDNodes is defined
to take a RegisterClass.

multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {

~Craig


On Mon, Feb 1, 2021 at 3:33 PM Paul C. Anagnostopoulos via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Yes, I can add a couple of lines of code to tgparser.cpp that will just
> check the types and complain if they aren't correct. I'll do that on
> Tuesday/Wednesday on Phabricator.
>
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