[llvm-dev] How to define subreg relationship in td file?

[林政宗 via llvm-dev]

Hi, there.




I met a problem about defining SubReg relationship when defining Registers in td file.

The target has a kind of vector register named VR which is of type v4f32.  

2 VR makes 1 DVR. 4 VR makes 1 QVR.

I have some code like this:

------------------------------------------------------------------------------------------------------

def VRPairs : RegisterTuples<[vsub_0, vsub_1],

                             [(decimate (rotl VRegs, 0), 2),

                              (decimate (rotl VRegs, 1), 2)],

                             []>;




def VRQuads : RegisterTuples<[vsub_0, vsub_1, vsub_2, vsub_3],

                             [(decimate (rotl VRegs, 0), 4),

                              (decimate (rotl VRegs, 1), 4),

                              (decimate (rotl VRegs, 2), 4),

                              (decimate (rotl VRegs, 3), 4)],

                             []>;

def DVRRegs : RegisterClass<"xxx", [v8f32], 256, (add VRPairs)>;

 

def QVRRegs : RegisterClass<"xxx", [v16f32], 512, (add VRQuads)>;

------------------------------------------------------------------------------------------------------

But also, 2 DVR makes 1 QVR. QVR has two subregs, each of which is 1 DVR.

How can I describe the SubReg relationship between DVR and QVR? 

Could anyone help? Thanks in advance!







BR,

Jerry
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