[llvm-dev] Implicit register move using TableGen

[Marco Speziali via llvm-dev]

Dear Craig,
Thanks for the reply. I tried to use the pattern you provided to set list<pattern> inside the ADD instruction. Unfortunately the pattern:

(set GPR:$rd, (add GPR:$rs1, R14))

Does not generate a move of $rs2 to R14. It, for some reason, produces an add with 3 register operands. Which we do not support. The only way to use 2 source registers is to move the second one to R14. For example:

add rd, rs1, rs2

Should become:

mv R14, rs2
add rd, rs1

Is there a way to automate this process using TableGen?

Thanks,
Marco Speziali

On 10 Apr 2021, at 19:09, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:

In tablegen you can write

(set GPR:$rd, (add GPR:$rs1, R14))

On Sat, Apr 10, 2021 at 9:19 AM Marco Speziali via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
Dear all,

I need to implement the following behavior for all instructions that
require two source operands:

%1 = add i16 %a, %b

Should match the ADD instruction which has 1 outs and 1 ins. The second
operand %b should be moved into the implicit register R14 (fixed).
For now I implemented the PseudoADD instruction which gets expanded into
a move plus the mentioned ADD instruction.
This obviously creates a low of unnecessary moves and prevents any
optimizations of the register R14 (e.g. R14 could be used as destination
register in previous operations without the need for a move).

I'd like to transform the dag:

(set GPR:$rd, (add GPR:$rs1, GPR:$rs2))

to something like:

(set R14, GPR:$rs2), (set GPR:$rd, (add GPR:$rs1))

Is it possible to specify this transformation using TableGen? If now how
could I achieve this?


Thanks.

Best Regards,
Marco Speziali

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