[llvm-dev] CPU-specific SVE codegen

[Craig Topper via llvm-dev]

Hi Chris,

I'm no an expert on SVE at all, but you might try the
"aarch64-sve-vector-bits-min" that was introduced in this patch
https://reviews.llvm.org/D80384  Myself and others have been basing a
similar feature for RISC-V off of this.

~Craig


On Sun, Apr 4, 2021 at 9:56 PM Chris Elrod via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Would it be possible to support generating CPU-specific SVE code?
> This could be useful for JIT, e.g. Julia.
>
> Currently, when using `-mcpu=a64fx`, `<8 x double>` gets split into 4 NEON
> instructions:
> https://godbolt.org/z/cEf1Pfvx8
> If I understand correctly, I'd need to use `<vscale x 2 x double>` to
> actually generate SVE code. However, Julia currently has no way of
> representing such variable sized types without allocating to the heap --
> awkward for a variable that's supposed to live in the registers! -- for
> writing intrinsics. Some libraries make extensive use of intrinsics
> operating on vector types like (`<8 x double>`) for defining compute
> kernels, and as is they are incompatible with SVE.
>
>
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