[llvm-dev] [riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?

[Michael Platzer via llvm-dev]

Hi Everyone,

I am wondering how to use RISC-V V (Vector) extension instructions in 
LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the 
Vector extension and on slide 16 [2] they show LLVM IR samples which use 
the vector instructions through intrinsic functions, such as:

%vl = call i32 @llvm.riscv.vsetvl(i32 %n)

At the time of the talk (April 2019) LLVM support for the V extension 
was developed out-of-tree at https://github.com/hanna-kruppe/rvv-llvm . 
However, that repository is archived now and the README file indicates 
that it is outdated since support for the RISC-V V extension is now 
developed upstream. I assume that this means that the features are now 
available from LLVM master.

However, when I pull the current master and build it and try to compile 
the sample code with llc (specifying the target with 
--mtriple=riscv32-unkown-none-rv32imv ), I get following error:

error: ../llvm-project/build/bin/llc: test.ll:4:18: error: use of 
undefined value '@llvm.riscv.vsetvl'

It seems that the V extension is available, since `llc -march=riscv32 
-mattr=help` lists it:

Available features for this target:
   ...
   experimental-v           - 'V' (Vector Instructions).

Do I have to explicitly enable intrinsics for target features that are 
marked as experimental? Are these vector intrinsics shown in the slides 
even present in the upstream version? If yes, how do I use them? If no, 
how do I then use vector instructions in LLVM IR?

Any hints would be greatly appreciated!

Thank you,
Michael

[1] 
https://llvm.org/devmtg/2019-04/slides/TechTalk-Kruppe-Espasa-RISC-V_Vectors_and_LLVM.pdf
[2] 
https://llvm.org/devmtg/2019-04/slides/TechTalk-Kruppe-Espasa-RISC-V_Vectors_and_LLVM.pdf#page=16

P.S: I asked this question on StackOverflow first ( 
https://stackoverflow.com/q/64099125/1404847 ), but am now asking on 
this list since I did not get a reply.