[llvm-dev] TableGen pseudo lowering

[Anton Korobeynikov via llvm-dev]

Oh, just take a look into e.g. ARM pseudo expansion pass
(lib/Target/ARM/ARMPseudoInsts.cpp). For example we could look into
expansion of MOV32Imm there (ExpandMOV32BitImm). Depending on the
operand various things needs to happen:
  - For Imm – just split imm into parts
  - For external symbol / GV – we need to add special target flags
(that will be translated to assembler modifiers or special kinds of
relocs)

Plus – we need to transfer the memory references, predicates, implicit
operands, etc.

Obviously, this is a "tough" case, though :)

On Sat, Sep 26, 2020 at 4:13 PM Paul C. Anagnostopoulos
<paul at windfall.com> wrote:
>
> Can you give an example of the property splitting issue?
>
> At 9/26/2020 03:34 AM, Anton Korobeynikov wrote:
> >Paul,
> >
> >Absolutely. This may reduce the amount of hand-written code for
> >pseudo-expansion in the backends in general. However, there are
> >caveats as in many cases additional properties need to be transferred
> >as well and "splitted" between these instructions. I don't have a good
> >solution for this.
> >
> >
> >On Fri, Sep 25, 2020 at 7:48 PM Paul C. Anagnostopoulos via llvm-dev
> ><llvm-dev at lists.llvm.org> wrote:
> >>
> >> The TableGen PseudoLoweringEmitter backend is responsible for lowering pseudo-instructions to real machine instructions. In the code is this comment:
> >>
> >> // FIXME: This pass currently can only expand a pseudo to a single instruction.
> >> //        The pseudo expansion really should take a list of dags, not just
> >> //        a single dag, so we can do fancier things.
> >>
> >> Does anyone think that enhancing it to expand to multiple instructions is worth the effort?
>


-- 
With best regards, Anton Korobeynikov
Department of Statistical Modelling, Saint Petersburg State University