[llvm-dev] Incorrect Cortex-R4/R4F/R5 ProcessorModel in ARM.td

[Peter Smith via llvm-dev]

Hello Alan,

Using a cortex-a8 scheduling model for v7-r CPUs may not be optimal but I wouldn't go as far as to call it incorrect. The cortex-r4, cortex-r4f and cortex-r5 are in-order cores like cortex-a8 (another in-order core) is the closest match. We don't have any current plans to develop a custom scheduling model for r4, r4f or r5.

Peter

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From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Phipps, Alan via llvm-dev <llvm-dev at lists.llvm.org>
Sent: 23 September 2020 15:27
To: llvm-dev at lists.llvm.org
Subject: [llvm-dev] Incorrect Cortex-R4/R4F/R5 ProcessorModel in ARM.td

In ARM.td, I see that the ProcessorModel for cortex-r4, cortex-r4f, and cortex-r5 (as well as r7 and r8) is based on “CortexA8Model”, which seems incorrect.  When this was added in 2015, there were also comments associated with this configuration, such as “// FIXME: R5 has currently the same ProcessorModel as A8” (later removed).  The processor model for Cortex-r52 appears to be correct and corresponds to an associated “CortexR52Model”.

Does anyone know why r4/r4f/r5 were setup based on “CortexA8Model”.

Is there a plan to upstream a fix to correct this?

Thanks!

Alan Phipps