[llvm-dev] Metadata in LLVM back-end

[Lorenzo Casalino via llvm-dev]

Am 31/08/20 um 14:10 schrieb David Greene:
> Lorenzo Casalino via llvm-dev <llvm-dev at lists.llvm.org> writes:
>
>> Furthermore, after register allocation there is a non-negligible effort
>> to properly annotate instructions which share the same output register...
>>
>> Concerning the usage of the live ranges to tie annotated instruction and
>> intrinsic, I have some doubts:
>>
>>  1. After register allocation, since metadata intrinsics are skipped
>> (otherwise,     they would be involved in the register allocation
>> process, increasing the     register pressure), the instruction stream
>> would present both virtual and     physical registers, which I am not
>> sure it is totally ok.
> They would have to participate in register allocation.
Should they? I mean: the register allocation "simply" creates a map
(VirtReg -> PhysReg),
and actual register re-writing takes place in a subsequent machine pass.

So, we could avoid their partecipation in register allocation, reducing
register
pressure and spill/reload work. As a downside, we would have
intrinsics with virtual registers as outputs, but it is not a problem,
since they do
not perform any real computation.
> I think the only
> downside would be an intrinsic that artificially extends the live range
> of a value by using it past its true dead point, either because the use
> really is the "last" one or because it fills a "hole" in the live range
> that otherwise would exist (for example a use in one of the if-then-else
> branches that would otherwise not exist).
>
> If the intrinsics really shadow "real" instructions then it should be
> possible to place them such that this is not an issue; for example, you
> could place them immediately before the "real" instruction.

I do not think this would be possible: before register allocation, code is
SSA form, thus the annotated instruction *must* preceeds the intrinsic
annotating it. An alternative is to place the annotating intrinsic before
the instruction who ends the specific live-range (not necessarely be an
immediate predecessor).

Just to point out a problem to cope with: instruction scheduling must be
aware of this particular positioning of annotation intrinsics.

> It's possible they could introduce extra spills and reloads, in that if
> a value is spilled it would be reloaded before the intrinsic.  If the
> intrinsic were placed immediately before the "real" instruction then the
> reload would very likely be re-used for the "real" instruction so this
> is probably not an issue in practice.

Yes, I agree


Kind regards,
-- Lorenzo