[llvm-dev] [riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?

[Sam Elliott via llvm-dev]

Michael,

Apologies for taking so long to get back to you.

Trunk LLVM does not contain support for code generating the V extension yet. The experimental-v support you see there is only MC-layer support, where you can use the V instructions in assembly (including inline assembly). There is currently (today) no way of turning LLVM IR vector intrinsics into RISC-V V extension instructions.

Hanna Kruppe did have a fork of LLVM where she and others were working on prototype support for the V extension. The work on support for the V extension has continued, but not via upstreaming the exact changes in that prototype - instead there is an RFC about code generation support: http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html <http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html> which includes links to proposed upstream patches implementing the RFC's approach.

I'm not sure the status of that RFC with respect to intrinsics for operations like vsetvl - but it seems likely to me that such an operation will be managed at a lower level than LLVM intrinsics. I hope someone like Roger or Evandro can chime in with their intentions with respect to this behaviour.

Sam


> On 29 Sep 2020, at 12:30 pm, Michael Platzer via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hi Everyone,
> 
> I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as:
> 
> %vl = call i32 @llvm.riscv.vsetvl(i32 %n)
> 
> At the time of the talk (April 2019) LLVM support for the V extension was developed out-of-tree at https://github.com/hanna-kruppe/rvv-llvm . However, that repository is archived now and the README file indicates that it is outdated since support for the RISC-V V extension is now developed upstream. I assume that this means that the features are now available from LLVM master.
> 
> However, when I pull the current master and build it and try to compile the sample code with llc (specifying the target with --mtriple=riscv32-unkown-none-rv32imv ), I get following error:
> 
> error: ../llvm-project/build/bin/llc: test.ll:4:18: error: use of undefined value '@llvm.riscv.vsetvl'
> 
> It seems that the V extension is available, since `llc -march=riscv32 -mattr=help` lists it:
> 
> Available features for this target:
>   ...
>   experimental-v           - 'V' (Vector Instructions).
> 
> Do I have to explicitly enable intrinsics for target features that are marked as experimental? Are these vector intrinsics shown in the slides even present in the upstream version? If yes, how do I use them? If no, how do I then use vector instructions in LLVM IR?
> 
> Any hints would be greatly appreciated!
> 
> Thank you,
> Michael
> 
> [1] https://llvm.org/devmtg/2019-04/slides/TechTalk-Kruppe-Espasa-RISC-V_Vectors_and_LLVM.pdf
> [2] https://llvm.org/devmtg/2019-04/slides/TechTalk-Kruppe-Espasa-RISC-V_Vectors_and_LLVM.pdf#page=16
> 
> P.S: I asked this question on StackOverflow first ( https://stackoverflow.com/q/64099125/1404847 ), but am now asking on this list since I did not get a reply.
> 
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--
Sam Elliott
Software Team Lead
Senior Software Developer - LLVM and OpenTitan
lowRISC CIC

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