[llvm-dev] RISC-V Custom Instruction Parsing Features

[Caool via llvm-dev]

Recently I have tried to introduce the RISC-V Platform in my workplace, 
and had to make some custom instructions within RISC-V ISA. When 
planning to set some custom value in ISA for our custom functions in our 
CPU, GNU toolchain offers .insn features to replace the opcodes with our 
value in it.

So I just wonder does clang/llvm support those features for developers 
to enable building the source/assembly with their own custom instruction 
value in it?