[llvm-dev] Tie output operand to subregister of input operand

[Dominik Montada via llvm-dev]

Hi,

I have an instruction that takes a 64-bit register as input and uses the 
lower 32-bit subregister as output. I am struggling to define the 
constraint in TableGen to make this work however.

Originally I had the following constraint:

let Constraint = "$dst = $src" in
def Foo : Instruction<..., (out GPR32:$dst), (ins GPR64:$src), ...>;

This however causes the following code to be produced:

%1:GPR32 = COPY %0:GPR64
%1:GPR32 = Foo %1:GPR32(tied-def 0)

Which causes an error, because the input to Foo must be a GPR64, not a 
GPR32.

I stumbled across complex operands, i.e. operands with suboperands:

def subregpair : Operand<i64> {
   let MIOperandInfo = (ops GPR32:$lo, GPR32:$hi);
}

let Constraint = "$dst = $src.lo" in
def Foo : Instruction<..., (out GPR32:$dst), (ins subregpair:$src), ...>;

However I'm not sure whether I'm using this correctly and if this is 
even the intended use-case for it, because I now get an error that Foo 
expects 2 operands, not 1.

Is this even doable in TableGen or will I need to manually fix up the 
registers somehow?

Cheers,

Dominik

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