[llvm-dev] TriviallyVectorizable Attribute in TD file

[Craig Topper via llvm-dev]

For the second part, I don't think most targets use type overloaded
intrinsics. For sure X86 doesn't. So in general they can't be vectorized by
just changing the type from scalar to vector. They would need to be
remapped to a different intrinsic name. The vectorize would also need to
avoid creating a type that the backend isn't prepared to see on a target
specific intrinsic.

~Craig


On Tue, Nov 24, 2020 at 1:34 PM Mark Schimmel via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> It seems wrong to me that VectorUtils.cpp contains this switch statement:
>
>
>
> /// Return true if all of the intrinsic's arguments and return type are
> scalars
>
> /// for the scalar form of the intrinsic, and vectors for the vector form
> of the
>
> /// intrinsic (except operands that are marked as always being scalar by
>
> /// hasVectorInstrinsicScalarOpd).
>
> bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
>
>   switch (ID) {
>
>   case Intrinsic::bswap: // Begin integer bit-manipulation.
>
>   case Intrinsic::bitreverse:
>
>
>
> First it would be easy to create an attribute for this that is defined in
> the TD file similar to others (IntrNoMem, IntrSpeculatable, IntrWillReturn,
> Commutative).
>
> Second, it should apply to target intrinsics and allow them to vectorize
> also.
>
>
>
> // Intrinsic isTriviallyVectorizable
>
> def TriviallyVectorizable : IntrinsicProperty;
>
>
>
> …
>
>
>
> Would you be open to a patch for this functionality?
>
>
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