[llvm-dev] BPF tablegen+codegen question

[Chris Sears via llvm-dev]

In BPF, an ADD instruction is defined as a 2 register instruction:

        0x0f.  add dst, src.  dst += src

In BPFInstrInfo.td this kind of ALU instruction is defined with:

        def _rr : ALU_RR<BPF_ALU64, Opc,
                   (outs GPR:$dst),
                   (ins GPR:$src2, GPR:$src),
                   "$dst "#OpcodeStr#" $src",
                   [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;

How does tablegen+codegen ensure that dst and src2 are the same register? I
see that the assembly/disassembly string assumes this is the case.

Also, it uses i64:$src which is an i64 and not a GPR. What is the
distinction there? X86 does this differently. src1 and src2 are GR64
registers.

        def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
                                   (ins GR64:$src1, GR64:$src2),
                  "imul{q}\t{$src2, $dst|$dst, $src2}",
                  [(set GR64:$dst, EFLAGS,
                        (X86smul_flag GR64:$src1, GR64:$src2))]>,
                  Sched<[WriteIMul64Reg]>, TB;

Chris
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