[llvm-dev] "Earlyclobber" but for a subset of the inputs

[Quentin Colombet via llvm-dev]

Hi Roger,

> On May 4, 2020, at 7:58 AM, Roger Ferrer Ibáñez via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hi all,
> 
> I'm working on a target whose registers have equal-sized subregisters and all of those subregisters can be named (or the other way round: registers can be grouped into super registers).
> 
> So for instance we've got 16 registers W (as in wide) W0..W15 and 32 registers N (as in narrow) N0..N31. This way, W0 is made by grouping N0 and N1, W1 is N2 and N3, W2 is N4 and N5, ..., W15 is N30 and N31.
> 
> The target has some widening instructions that take a number of N registers and output a W register. Possible combinations are
> 
> Wdest = widen-op Nsrc1, Nsrc2
> Wdest = widen-op Wsrc1, Nsrc2
> 
> The target constraints that the output register of these instructions cannot overlap, physically, an input of a different kind (W vs N).
> 
> For instance:
> 
> W1 = widen-op N4, N5  [this is ok, W1 is (N2, N3), so no overlap]
> W1 = widen-op N3, N4 [this is wrong because W1 is (N2, N3), thus overlap]
> W1 = widen-op W1, N4 [this is OK, W1 does not overlap with N4]

It sounds like you only need the earlyclobber description for the N, N variant.
In other words, as long as you use different opcodes for widen-op NN and widen-op WN, you model exactly what you want.

What am I missing?

Cheers,
-Quentin 

> 
> I can model these constraints using @earlyclobber and it works great for the `Wdest = widen-op Nsrc1, Nsrc2` case. While correct, this is suboptimal for the `Wdest = widen-op Wsrc1, Nsrc2` case because RA will never assign registers as in:
> 
> W1 = widen-op W1, N4 [RegAlloc would do something like W3 = widen-op W1, N4]
> 
> Has anyone encountered a similar situation? Perhaps all this can be modelled in a more obvious way?
> 
> Thank you very much,
> 
> -- 
> Roger Ferrer Ibáñez
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