[llvm-dev] Getting up to speed with llvm backends. Machine Instruction operands.
David Greene via llvm-dev
llvm-dev at lists.llvm.org
Thu Mar 12 12:45:48 PDT 2020
Anton Korobeynikov <anton at korobeynikov.info> writes:
>> Yes. The AArch64 backend might be a good guide as it supports pre- and
>> post-increment. I don't know if any existing target has
>> pointer-to-pointer operands (that's kind of a strange thing as it
>> requires two memory operands in one instruction) but I don't think it
>> would be super difficult to add. The X86 backend has special matching
>> code to construct its more complex addressing modes.
> MSP430 has memory-memory instructions. As well as post-increments.
> Probably the smallest backend to check :)
I mistyped :). My understanding is the with the pointer-to-pointer
operand the instruction would issues two memory *operations* (not have
two memory *operands* as I had written). That is, the DAG to match
would be a load from an address produced by another load.
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