[llvm-dev] Manipulating Arch specific code generator state

Sjoerd Meijer via llvm-dev llvm-dev at lists.llvm.org
Mon Mar 9 14:18:34 PDT 2020

I am unfamiliar with that architecture and ISA, but quite a few architectures have a status register and flag setting/reading instructions. You can probably get inspiration from the X86, ARM or MIPS backends. Again, not entirely sure how your situation is different, but I guess you don't want to store that in machineblocks because it is something that instructions produce/consume.
From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of connor horman via llvm-dev <llvm-dev at lists.llvm.org>
Sent: 09 March 2020 12:31
To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
Subject: [llvm-dev] Manipulating Arch specific code generator state

Hello all on the list,
I’m developing a backend for the 65816, however, I need a way to store some state, as processor flags can affect how instructions operate (including the length of some), as well as the calling convention. I need to track for each of these flags (x, m, and e) Set, Unset, Indeterminate. I was wondering if there was a nice way to store this with the MBB, so I can make sure everything does the right thing, and emit code to ensure the correct mode when necessary.
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