[llvm-dev] Why doesn't this `and` get eliminated

[Riyaz Puthiyapurayil via llvm-dev]

Oops! My bad! The code I intended to write was:
define dso_local i32 @f(i3 %0) {
    %2 = and i3 %0, 7
  %3 = icmp eq i3 %2, 7
  %4 = zext i1 %3 to i32
  ret i32 %4
}

The `and` does get removed in this case as expected. Thanks for answering the dumb question. 😊

/Riyaz

From: Craig Topper <craig.topper at gmail.com>
Sent: Thursday, June 11, 2020 6:57 PM
To: Riyaz Puthiyapurayil <riyaz at synopsys.com>
Cc: llvm-dev <llvm-dev at lists.llvm.org>
Subject: Re: [llvm-dev] Why doesn't this `and` get eliminated

I don't think its legal to remove it. That code is equivalent to asking (%0 mod 8) == 7. Which is true for 7 and 15 and 23, etc. You can't just remove the mod part of that or it would just return true for %0 == 7.

~Craig


On Thu, Jun 11, 2020 at 6:31 PM Riyaz Puthiyapurayil via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
define dso_local i32 @f(i32 %0) {
  %2 = and i32 %0, 7
  %3 = icmp eq i32 %2, 7
  %4 = zext i1 %3 to i32
  ret i32 %4
}

I thought instcombine would remove it. It doesn’t and nothing else does either. LLVM Version is 10.0.0.

/Riyaz
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