[llvm-dev] [AArch64][SVE] Floating Point Code Gen

[Danilo Carvalho Grael via llvm-dev]

Hello,

I am following up on the issue discussed at the SVE meeting, Sander
mentioned that there were some patterns missing from SVE CodeGen for
floating point operations, but I was unable to identify them.

He mentioned something about looking at the ISelLowering for AArch64 to
identify them, so if there is any information of that regard it would be
greatly appreciated so we can contribute with the missing patterns that
will be required later on when fixed-width vectors are implemented.

Best regards,
Danilo Carvalho Grael
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200615/df8a7033/attachment.html>