[llvm-dev] Nested instruction patterns rejected by GlobalISel when having registers in Defs

[Gabriel Hjort Åkerlund via llvm-dev]

Hi,



I am in the process of porting our target to GlobalISel, and have encountered a problem. Nearly all instructions in our instruction set make modifications to a CC register, and hence are defined as follows:



let ..., Defs = [CCReg] in

def shfts_a32_imm7: Instruction<(outs OurRC:$dst), ...>;



What's more, many of these instructions have patterns where the instruction itself appears inside a nested tree, e.g.:



def Pat<(source pattern ...),

        (sext_a32 (INSERT_SUBREG (...), (shfts_a32_imm7 OurRC:$src, Imm7:$imm), ...>;



Now to the problem: When TableGen processes the instruction above, it includes the CCReg in the Defs field along with the registers appearing in outs, thereby indicating that shfts_a32_imm7 produces two results. Currently, the GlobalISel-backend in TableGen requires that nested instructions appearing in the output pattern produce exactly one result. Consequently, TableGen rejects many of our patterns. But in reality, the instruction really only produces a single result and therefore this pattern should be allowed.



So I wonder, how should registers appear in Defs be treated? Are they equal to those appearing in outs, and therefore interchangeable, or is it valid to disambiguate between them and therefore modify TableGen to only consider outs as the result of interest when processing the patterns?



Gabriel Hjort Åkerlund



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