[llvm-dev] [RFC] Saturating left shift intrinsics

[Bevin Hansson via llvm-dev]

My idea is definitely to add support in the optimizer for them, but I don’t know quite yet to what extent. Constant folding and simplification of known (non-)saturating operations seems reasonable to add.

I’m also not sure when I will get to it; I would like to get the Clang patches in first, but those are a bit blocked by other refactorings at the moment.

From: Nikita Popov <nikita.ppv at gmail.com>
Sent: July 16, 2020 22:31
To: Bevin Hansson <bevin.hansson at ericsson.com>
Cc: llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] [RFC] Saturating left shift intrinsics

On Wed, Jul 8, 2020 at 5:31 PM Bevin Hansson via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
Hello,

This is an RFC for adding intrinsics which perform saturating signed/unsigned left shift.
There is currently a patch on Phabricator here:
https://reviews.llvm.org/D83216

The intrinsics are of the form

    i32 @llvm.sshl.sat.i32(i32, i32)
    i32 @llvm.ushl.sat.i32(i32, i32)
    <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
    <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32>, <4 x i32>)

and are overloaded with a single type which can be either an integer type or a vector of integers. The value(s) provided in the first operand are shifted left by the amount(s) given by the second operand. As with regular left shift instructions, the second operand is an unsigned quantity and must be less than the integer bitwidth.

If the true result of the operation (given infinite precision) lies outside of the maximum or minimum representable value of the signed/unsigned integer, the result saturates to the maximum or minimum depending on the sign of the shifted value.

These are useful for implementing the Embedded-C fixed-point arithmetic support in Clang, as previously detailed and discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-August/125433.html
http://lists.llvm.org/pipermail/cfe-dev/2018-May/058019.html

It is of course possible to emit these shifts as regular IR instructions, but targets which support saturating shifts might have difficulties efficiently selecting native instructions if the optimizer undoes the particular expected instruction pattern that the shifts would be selected on.

These generally look reasonable to me, and fit in with the existing saturating arithmetic intrinsics. My only question here would be what kind of support these intrinsics are targeting.

Are you planning to work on high-quality middle end support for them, with an eventual goal of canonicality (as is the case for the existing saturating arithmetic intrinsics), or are these intended to be target intrinsics in all but name (as is the case for the existing fixed-point intrinsics)?

Regards,
Nikita
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